microwave_timer.vhd

该芯片的功能是： ① 有一复位开关

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity microwave_timer is
  port(clk       : in std_logic;
       reset     : in std_logic;
       data      : in std_logic_vector(15 downto 0);
       test      : in std_logic;
       set_time  : in std_logic;
       start_cook: in std_logic;
       cook      : out std_logic;
       min_msb   : out std_logic_vector(1 to 7);
       min_lsb   : out std_logic_vector(1 to 7);
       sec_msb   : out std_logic_vector(1 to 7);
       sec_lsb   : out std_logic_vector(1 to 7));
end microwave_timer;
architecture structure of microwave_timer is
    component state_control is   
     port(clk  : in std_logic;
          done : in std_logic;
          reset: in std_logic;
          test : in std_logic;
          set_time: in std_logic;
          start_cook:in std_logic;
          cook:out std_logic;
          load_8888:out std_logic;
          load_clk:out std_logic;
          load_done:out std_logic);
    end component;
  
    component loader is
     port( data: in std_logic_vector(15 downto 0);
           load_8888:in std_logic;
           load_clk:in std_logic;
           load_done:in std_logic;
           load:out std_logic;
           load_val:out std_logic_vector(15 downto 0));
    end component;

    component timer is
        port (clk       : in  std_logic;
              data      : in  std_logic_vector(15 downto 0);
              down      : in  std_logic;
              load      : in  std_logic;
              done      : out std_logic;
              min_msb   : out std_logic_vector(1 to 7);
              min_lsb   : out std_logic_vector(1 to 7);
              sec_msb   : out std_logic_vector(1 to 7);
              sec_lsb   : out std_logic_vector(1 to 7));
    end component;
    signal data_tmp :std_logic_vector(15 downto 0);
    signal cook_tmp :std_logic;
    signal load_8888:std_logic;
    signal load_clk :std_logic;
    signal load_done:std_logic;
    signal load     :std_logic;
    signal  done     :std_logic;
begin
    cook<=cook_tmp;
    u0: state_control
        port map(clk=>clk,done=>done,reset=>reset,test=>test,set_time=>set_time,
                 start_cook=>start_cook,cook=>cook_tmp,load_8888=>load_8888,load_clk=>load_clk,load_done=>load_done);
    u1: loader
        port map(data=>data,load_8888=>load_8888,load_clk=>load_clk,load_done=>load_done,load=>load,load_val=>data_tmp);
    u2: timer
        port map(clk=>clk,data=>data_tmp,down=>cook_tmp,load=>load,done=>done,min_msb=>min_msb,min_lsb=>min_lsb,
                 sec_msb=>sec_msb,sec_lsb=>sec_lsb);
end structure;