timer.vhd

该芯片的功能是： ① 有一复位开关

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity timer is
  port (clk       : in  std_logic;
        data      : in  std_logic_vector(15 downto 0);
        down      : in  std_logic;
        load      : in  std_logic;
        done      : out std_logic;
        min_msb   : out std_logic_vector(1 to 7);
        min_lsb   : out std_logic_vector(1 to 7);
        sec_msb   : out std_logic_vector(1 to 7);
        sec_lsb   : out std_logic_vector(1 to 7));
end timer;
architecture timer_arc of timer is
    component counter4 is
      port(clk     : in std_logic;
           cnt_f_5 : in std_logic;
           data_in : in std_logic_vector(3 downto 0);   
           down    : in std_logic;
           load    : in std_logic;
           zero    : out std_logic; 
           segs    : out std_logic_vector(1 to 7));
    end component;
    signal zer0,zer1,zer2,zer3 : std_logic;
    signal down0,down1,down2,down3 : std_logic;
    signal data0,data1,data2,data3 : std_logic_vector(3 downto 0);
    signal is_five,is_nine : std_logic;
begin
    is_five<='1';
    is_nine<='0'; 
    data3<=data(15 downto 12);
    data2<=data(11 downto 8);
    data1<=data(7 downto 4);
    data0<=data(3 downto 0);
    process(zer0,zer1,zer2,zer3,down)
    begin  
      done<=zer3 and zer2 and zer1 and zer0;
      down3<='0';
      down2<='0';
      down1<='0'; 
      down0<='0';
      if(down='1') then
         down0<='1';
      end if;
      if (zer0='1') then
         down1<='1';
      end if;
      if(zer1='1')then
        down2<='1';
      end if;
      if(zer2='1') then
        down3<='1';
      end if;
     end process;
     u3:counter4 
        port map(clk=>clk,cnt_f_5=>is_five,data_in=>data3,down=>down3,load=>load,zero=>zer3,segs=>min_msb);
     u2:counter4
        port map(clk=>clk,cnt_f_5=>is_nine,data_in=>data2,down=>down2,load=>load,zero=>zer2,segs=>min_lsb);
     u1:counter4
        port map(clk=>clk,cnt_f_5=>is_five,data_in=>data1,down=>down1,load=>load,zero=>zer1,segs=>sec_msb);
     u0:counter4
        port map(clk=>clk,cnt_f_5=>is_nine,data_in=>data0,down=>down0,load=>load,zero=>zer0,segs=>sec_lsb);
end timer_arc;