microwave_timer.map.rpt

该芯片的功能是： ① 有一复位开关

+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |microwave_timer|timer:u2|counter4:u0|dual_reg4:u3|q[0] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |microwave_timer|timer:u2|counter4:u1|dual_reg4:u3|q[0] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |microwave_timer|timer:u2|counter4:u2|dual_reg4:u3|q[2] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |microwave_timer|timer:u2|counter4:u3|dual_reg4:u3|q[0] ;
; 3:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |microwave_timer|loader:u1|Mux12                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Thu Sep 27 16:01:57 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off microwave_timer -c microwave_timer
Info: Found 2 design units, including 1 entities, in source file bcd7.vhd
    Info: Found design unit 1: bcd7-rtl
    Info: Found entity 1: bcd7
Info: Found 2 design units, including 1 entities, in source file counter4.vhd
    Info: Found design unit 1: counter4-structure
    Info: Found entity 1: counter4
Info: Found 2 design units, including 1 entities, in source file decr4.vhd
    Info: Found design unit 1: decr4-rtl
    Info: Found entity 1: decr4
Info: Found 2 design units, including 1 entities, in source file dual_reg4.vhd
    Info: Found design unit 1: dual_reg4-rtl
    Info: Found entity 1: dual_reg4
Info: Found 2 design units, including 1 entities, in source file loader.vhd
    Info: Found design unit 1: loader-loader_arc
    Info: Found entity 1: loader
Info: Found 2 design units, including 1 entities, in source file microwave_timer.vhd
    Info: Found design unit 1: microwave_timer-structure
    Info: Found entity 1: microwave_timer
Info: Found 3 design units, including 1 entities, in source file state_control.vhd
    Info: Found design unit 1: state_pack
    Info: Found design unit 2: state_control-state_control_arc
    Info: Found entity 1: state_control
Info: Found 2 design units, including 1 entities, in source file timer.vhd
    Info: Found design unit 1: timer-timer_arc
    Info: Found entity 1: timer
Info: Found 2 design units, including 1 entities, in source file zero_detect.vhd
    Info: Found design unit 1: zero_detect-rtl
    Info: Found entity 1: zero_detect
Info: Elaborating entity "microwave_timer" for the top level hierarchy
Info: Elaborating entity "state_control" for hierarchy "state_control:u0"
Info: Elaborating entity "loader" for hierarchy "loader:u1"
Warning (10631): VHDL Process Statement warning at loader.vhd(14): inferring latch(es) for signal or variable "load_val", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[0]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[1]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[2]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[3]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[4]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[5]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[6]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[7]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[8]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[9]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[10]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[11]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[12]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[13]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[14]"
Info (10041): Verilog HDL or VHDL info at loader.vhd(14): inferred latch for "load_val[15]"
Info: Elaborating entity "timer" for hierarchy "timer:u2"
Info: Elaborating entity "counter4" for hierarchy "timer:u2|counter4:u3"
Info: Elaborating entity "zero_detect" for hierarchy "timer:u2|counter4:u3|zero_detect:u0"
Info: Elaborating entity "bcd7" for hierarchy "timer:u2|counter4:u3|bcd7:u1"
Info: Elaborating entity "decr4" for hierarchy "timer:u2|counter4:u3|decr4:u2"
Info: Elaborating entity "dual_reg4" for hierarchy "timer:u2|counter4:u3|dual_reg4:u3"
Info: State machine "|microwave_timer|state_control:u0|current_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|microwave_timer|state_control:u0|current_state"
Info: Encoding result for state machine "|microwave_timer|state_control:u0|current_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "state_control:u0|current_state.done_msg"
        Info: Encoded state bit "state_control:u0|current_state.timer"
        Info: Encoded state bit "state_control:u0|current_state.set_clock"
        Info: Encoded state bit "state_control:u0|current_state.lamp_test"
        Info: Encoded state bit "state_control:u0|current_state.idle"
    Info: State "|microwave_timer|state_control:u0|current_state.idle" uses code string "00000"
    Info: State "|microwave_timer|state_control:u0|current_state.lamp_test" uses code string "00011"
    Info: State "|microwave_timer|state_control:u0|current_state.set_clock" uses code string "00101"
    Info: State "|microwave_timer|state_control:u0|current_state.timer" uses code string "01001"
    Info: State "|microwave_timer|state_control:u0|current_state.done_msg" uses code string "10001"
Warning: Latch loader:u1|load_val[12] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[13] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[14] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[15] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.done_msg
Warning: Latch loader:u1|load_val[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Warning: Latch loader:u1|load_val[11] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal state_control:u0|current_state.set_clock
Info: Implemented 183 device resources after synthesis - the final resource count might be different
    Info: Implemented 21 input pins
    Info: Implemented 29 output pins
    Info: Implemented 133 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings
    Info: Allocated 139 megabytes of memory during processing
    Info: Processing ended: Thu Sep 27 16:02:00 2007
    Info: Elapsed time: 00:00:03