counter4.vhd

来自「该芯片的功能是： ① 有一复位开关」· VHDL 代码 · 共 46 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counter4 is
   port(clk:in std_logic;
        cnt_f_5:in std_logic;
        data_in:in std_logic_vector(3 downto 0);   
        down:in std_logic;
        load:in std_logic;
        zero:out std_logic; 
        segs:out std_logic_vector(1 to 7));
end counter4;
architecture structure of counter4 is
   component zero_detect is
     port(a: in std_logic_vector(3 downto 0);
          zero:out std_logic);
   end component;
   component bcd7 is
     port(q:in std_logic_vector(3 downto 0);
          segments:out std_logic_vector(1 to 7));
   end component;
   component decr4 is
     port(cnt_f_5:in std_logic;
          dec_in:in std_logic_vector(3 downto 0);
          dec_out:out std_logic_vector(3 downto 0));
   end component;
   component dual_reg4 is
     port(a:in std_logic_vector(3 downto 0);
          b:in std_logic_vector(3 downto 0);
          clk:in std_logic;
          lda:in std_logic;
          ldb:in std_logic;
          q:out std_logic_vector(3 downto 0));
   end component; 
   signal count:std_logic_vector(3 downto 0);
   signal temp:std_logic_vector(3 downto 0);
begin
   u0:zero_detect
      port map (a=>count,zero=>zero);
   u1:bcd7
      port map(q=>count,segments=>segs);
   u2:decr4
      port map(cnt_f_5=>cnt_f_5,dec_in=>count,dec_out=>temp);
   u3:dual_reg4
      port map(a=>data_in,b=>temp,clk=>clk,lda=>load,ldb=>down,q=>count);
end structure;