📄 main.dbg
字号:
;*******************************************************************
;* This stationery serves as the framework for a user application. *
;* For a more comprehensive program that demonstrates the more *
;* advanced functionality of this processor, please see the *
;* demonstration applications, located in the examples *
;* subdirectory of the "Freescale CodeWarrior for HC08" program *
;* directory. *
;*******************************************************************
; export symbols
XDEF _Startup, main
; we export both '_Startup' and 'main' as symbols. Either can
; be referenced in the linker .prm file or from C/C++ later on
; Include derivative-specific definitions
INCLUDE 'derivative.inc'
; Note: This file is recreated by the project wizard whenever the MCU is
; changed and should not be edited by hand
; include derivative specific macros
INCLUDE 'MC9RS08KA2.inc'
; Based on CPU DB MC9RS08KA2_8, version 2.87.036 (RegistersPrg V2.05)
; ###################################################################
; Filename : MC9RS08KA2.inc
; Processor : MC9RS08KA2DN
; FileFormat: V2.05
; DataSheet : MC9RS08KA2 Rev. 0.09 03/10/2006
; Compiler : CodeWarrior compiler
; Date/Time : 30.03.2006, 15:19
; Abstract :
; This header implements the mapping of I/O devices.
;
; (c) Copyright UNIS, spol. s r.o. 1997-2006
; UNIS, spol. s r.o.
; Jundrovska 33
; 624 00 Brno
; Czech Republic
; http : www.processorexpert.com
; mail : info@processorexpert.com
;
; File-Format-Revisions:
; - 24.03.2006, V2.05 :
; - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order.
;
; CPU Registers Revisions:
; - none
; ###################################################################
;*** Memory Map
;******************************************
TINY_RAMStart: equ $00000000
TINY_RAMEnd: equ $0000000D
RAMStart: equ $00000020
RAMEnd: equ $0000004F
ROMStart: equ $00003800
ROMEnd: equ $00003FF7
RESET_JMP_AREAStart: equ $00003FFD
RESET_JMP_AREAEnd: equ $00003FFF
;
;
;*** PTAD - Port A Data Register; 0x00000010 ***
PTAD: equ $00000010 ;*** PTAD - Port A Data Register; 0x00000010 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTAD_PTAD0: equ 0 ; Port A Data Register Bit 0
PTAD_PTAD1: equ 1 ; Port A Data Register Bit 1
PTAD_PTAD2: equ 2 ; Port A Data Register Bit 2
PTAD_PTAD3: equ 3 ; Port A Data Register Bit 3
PTAD_PTAD4: equ 4 ; Port A Data Register Bit 4
PTAD_PTAD5: equ 5 ; Port A Data Register Bit 5
; bit position masks
mPTAD_PTAD0: equ %00000001
mPTAD_PTAD1: equ %00000010
mPTAD_PTAD2: equ %00000100
mPTAD_PTAD3: equ %00001000
mPTAD_PTAD4: equ %00010000
mPTAD_PTAD5: equ %00100000
;*** PTADD - Data Direction Register A; 0x00000011 ***
PTADD: equ $00000011 ;*** PTADD - Data Direction Register A; 0x00000011 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PTADD_PTADD0: equ 0 ; Data Direction for Port A Bit 0
PTADD_PTADD1: equ 1 ; Data Direction for Port A Bit 1
PTADD_PTADD4: equ 4 ; Data Direction for Port A Bit 4
PTADD_PTADD5: equ 5 ; Data Direction for Port A Bit 5
; bit position masks
mPTADD_PTADD0: equ %00000001
mPTADD_PTADD1: equ %00000010
mPTADD_PTADD4: equ %00010000
mPTADD_PTADD5: equ %00100000
;*** ACMPSC - Analog Comparator Status and Control Register; 0x00000013 ***
ACMPSC: equ $00000013 ;*** ACMPSC - Analog Comparator Status and Control Register; 0x00000013 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ACMPSC_ACMOD0: equ 0 ; Analog Comparator Mode Bit 0
ACMPSC_ACMOD1: equ 1 ; Analog Comparator Mode Bit 1
ACMPSC_ACOPE: equ 2 ; Analog Comparator Output Pin Enable
ACMPSC_ACO: equ 3 ; Analog Comparator Output
ACMPSC_ACIE: equ 4 ; Analog Comparator Interrupt Enable
ACMPSC_ACF: equ 5 ; Analog Comparator Flag
ACMPSC_ACBGS: equ 6 ; Analog Comparator Bandgap Select
ACMPSC_ACME: equ 7 ; Analog Comparator Module Enable
; bit position masks
mACMPSC_ACMOD0: equ %00000001
mACMPSC_ACMOD1: equ %00000010
mACMPSC_ACOPE: equ %00000100
mACMPSC_ACO: equ %00001000
mACMPSC_ACIE: equ %00010000
mACMPSC_ACF: equ %00100000
mACMPSC_ACBGS: equ %01000000
mACMPSC_ACME: equ %10000000
;*** ICSC1 - ICS Control Register 1; 0x00000014 ***
ICSC1: equ $00000014 ;*** ICSC1 - ICS Control Register 1; 0x00000014 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC1_IREFSTEN: equ 0 ; Internal Reference Stop Enable
ICSC1_CLKS: equ 6 ; Clock Source Select
; bit position masks
mICSC1_IREFSTEN: equ %00000001
mICSC1_CLKS: equ %01000000
;*** ICSC2 - ICS Control Register 2; 0x00000015 ***
ICSC2: equ $00000015 ;*** ICSC2 - ICS Control Register 2; 0x00000015 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSC2_LP: equ 3 ; Low Power Select
ICSC2_BDIV: equ 6 ; Bus Frequency Divider
; bit position masks
mICSC2_LP: equ %00001000
mICSC2_BDIV: equ %11000000
;*** ICSTRM - ICS Trim Register; 0x00000016 ***
ICSTRM: equ $00000016 ;*** ICSTRM - ICS Trim Register; 0x00000016 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSTRM_TRIM: equ 0 ; ICS Trim Setting
; bit position masks
mICSTRM_TRIM: equ %11111111
;*** ICSSC - ICS Status and Control; 0x00000017 ***
ICSSC: equ $00000017 ;*** ICSSC - ICS Status and Control; 0x00000017 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
ICSSC_FTRIM: equ 0 ; ICS Fine Trim
ICSSC_CLKST: equ 2 ; Clock Mode Status
; bit position masks
mICSSC_FTRIM: equ %00000001
mICSSC_CLKST: equ %00000100
;*** MTIMSC - MTIM Status and Control Register; 0x00000018 ***
MTIMSC: equ $00000018 ;*** MTIMSC - MTIM Status and Control Register; 0x00000018 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MTIMSC_TSTP: equ 4 ; MTIM Counter Stop
MTIMSC_TRST: equ 5 ; MTIM Counter Reset
MTIMSC_TOIE: equ 6 ; MTIM Overflow Interrupt Enable
MTIMSC_TOF: equ 7 ; MTIM Overflow Flag
; bit position masks
mMTIMSC_TSTP: equ %00010000
mMTIMSC_TRST: equ %00100000
mMTIMSC_TOIE: equ %01000000
mMTIMSC_TOF: equ %10000000
;*** MTIMCLK - MTIM Clock Configuration Register; 0x00000019 ***
MTIMCLK: equ $00000019 ;*** MTIMCLK - MTIM Clock Configuration Register; 0x00000019 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
MTIMCLK_PS: equ 0 ; Clock Source Prescaler
MTIMCLK_CLKS: equ 4 ; Clock Source Select
; bit position masks
mMTIMCLK_PS: equ %00001111
mMTIMCLK_CLKS: equ %00110000
;*** MTIMCNT - MTIM Counter Register; 0x0000001A ***
MTIMCNT: equ $0000001A ;*** MTIMCNT - MTIM Counter Register; 0x0000001A ***
;*** MTIMMOD - MTIM Modulo Register; 0x0000001B ***
MTIMMOD: equ $0000001B ;*** MTIMMOD - MTIM Modulo Register; 0x0000001B ***
;*** KBISC - KBI Status and Control; 0x0000001C ***
KBISC: equ $0000001C ;*** KBISC - KBI Status and Control; 0x0000001C ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBISC_KBIMOD: equ 0 ; Keyboard Detection Mode
KBISC_KBIE: equ 1 ; Keyboard Interrupt Enable
KBISC_KBACK: equ 2 ; Keyboard Interrupt Acknowledge
KBISC_KBF: equ 3 ; Keyboard Interrupt Flag
; bit position masks
mKBISC_KBIMOD: equ %00000001
mKBISC_KBIE: equ %00000010
mKBISC_KBACK: equ %00000100
mKBISC_KBF: equ %00001000
;*** KBIPE - KBI Pin Enable Register; 0x0000001D ***
KBIPE: equ $0000001D ;*** KBIPE - KBI Pin Enable Register; 0x0000001D ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBIPE_KBIPE0: equ 0 ; Keyboard Pin Enable for Port A Bit 0
KBIPE_KBIPE1: equ 1 ; Keyboard Pin Enable for Port A Bit 1
KBIPE_KBIPE2: equ 2 ; Keyboard Pin Enable for Port A Bit 2
KBIPE_KBIPE4: equ 4 ; Keyboard Pin Enable for Port A Bit 4
KBIPE_KBIPE5: equ 5 ; Keyboard Pin Enable for Port A Bit 5
; bit position masks
mKBIPE_KBIPE0: equ %00000001
mKBIPE_KBIPE1: equ %00000010
mKBIPE_KBIPE2: equ %00000100
mKBIPE_KBIPE4: equ %00010000
mKBIPE_KBIPE5: equ %00100000
;*** KBIES - KBI Edge Select Register; 0x0000001E ***
KBIES: equ $0000001E ;*** KBIES - KBI Edge Select Register; 0x0000001E ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
KBIES_KBEDG0: equ 0 ; Keyboard Edge Select Bit 0
KBIES_KBEDG1: equ 1 ; Keyboard Edge Select Bit 1
KBIES_KBEDG2: equ 2 ; Keyboard Edge Select Bit 2
KBIES_KBEDG4: equ 4 ; Keyboard Edge Select Bit 4
KBIES_KBEDG5: equ 5 ; Keyboard Edge Select Bit 5
; bit position masks
mKBIES_KBEDG0: equ %00000001
mKBIES_KBEDG1: equ %00000010
mKBIES_KBEDG2: equ %00000100
mKBIES_KBEDG4: equ %00010000
mKBIES_KBEDG5: equ %00100000
;*** PAGESEL - Page Register; 0x0000001F ***
PAGESEL: equ $0000001F ;*** PAGESEL - Page Register; 0x0000001F ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
PAGESEL_AD6: equ 0 ; Page Selector Bit 6
PAGESEL_AD7: equ 1 ; Page Selector Bit 7
PAGESEL_AD8: equ 2 ; Page Selector Bit 8
PAGESEL_AD9: equ 3 ; Page Selector Bit 9
PAGESEL_AD10: equ 4 ; Page Selector Bit 10
PAGESEL_AD11: equ 5 ; Page Selector Bit 11
PAGESEL_AD12: equ 6 ; Page Selector Bit 12
PAGESEL_AD13: equ 7 ; Page Selector Bit 13
; bit position masks
mPAGESEL_AD6: equ %00000001
mPAGESEL_AD7: equ %00000010
mPAGESEL_AD8: equ %00000100
mPAGESEL_AD9: equ %00001000
mPAGESEL_AD10: equ %00010000
mPAGESEL_AD11: equ %00100000
mPAGESEL_AD12: equ %01000000
mPAGESEL_AD13: equ %10000000
;*** SRS - System Reset Status Register; 0x00000200 ***
SRS: equ $00000200 ;*** SRS - System Reset Status Register; 0x00000200 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SRS_LVD: equ 1 ; Low Voltage Detect
SRS_ILAD: equ 3 ; Illegal Address
SRS_ILOP: equ 4 ; Illegal Opcode
SRS_COP: equ 5 ; Computer Operating Properly (COP) Watchdog
SRS_PIN: equ 6 ; External Reset Pin
SRS_POR: equ 7 ; Power-On Reset
; bit position masks
mSRS_LVD: equ %00000010
mSRS_ILAD: equ %00001000
mSRS_ILOP: equ %00010000
mSRS_COP: equ %00100000
mSRS_PIN: equ %01000000
mSRS_POR: equ %10000000
;*** SOPT - System Options Register; 0x00000201 ***
SOPT: equ $00000201 ;*** SOPT - System Options Register; 0x00000201 ***
; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
SOPT_RSTPE: equ 0 ; RESET Pin Enable
SOPT_BKGDPE: equ 1 ; Background Debug Mode Pin Enable
SOPT_STOPE: equ 5 ; Stop Mode Enable
SOPT_COPT: equ 6 ; COP Watchdog Timeout
SOPT_COPE: equ 7 ; COP Watchdog Enable
; bit position masks
mSOPT_RSTPE: equ %00000001
mSOPT_BKGDPE: equ %00000010
mSOPT_STOPE: equ %00100000
mSOPT_COPT: equ %01000000
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -