qsnesdoc.html

SNES game emulator. C and asm files.

<PRE>dddddddd&nbsp; d: byte that was read from CGRAM</PRE>
After the byte is read, the CGRAM address is incremented so that the next
write or read will be to the following byte.
<CENTER>&nbsp;</CENTER>

<CENTER><A NAME="RegVRAM"></A><FONT SIZE=+2>VRAM Transfer/Address Registers</FONT></CENTER>


<P><A NAME="Reg2107"></A><B><FONT FACE="Lucida Console">Register $2107-$210A:
Tile map location (4*1B/W)</FONT></B>
<PRE>Bits in each of the registers:
aaaaaass&nbsp; a: Tile map address&nbsp; s: SC size: 00=32x32 01=64x32
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 10=32x64 11=64x64</PRE>
To calculate the byte location where the tile map starts, shift the a (address)
bits left by 11 (multiply by 2048.)&nbsp; The SC size is the dimensions
of the tile map; if using 8x8 tile mode, this allows BG dimensions of 256
or 512 pixels; if in 16x16 mode, the dimensions can be 512 or 1024 pixels.&nbsp;
Note that, since there is only 64K of VRAM, the most significant bit must
be zero.

<P>When using a screen size wider than 32 tiles, the format is a little
different than you might expect.&nbsp; When the width is 64 tiles, then
rather than each line in the tile map extending to 128 bytes (instead of
64), there will actually be <I>two</I> tile maps, stored one right after
the other in memory.&nbsp; The first tile map will contain the left 32
tiles (x coordinates 0 to 255, when using 8x8 tiles), and the next tile
map will contain the right 32 tiles (x coordinates 256 to 511, when using
8x8 tiles. Setting the scroll register to 512, then, will be the same at
setting it to zero.)

<P>A note about using 16x16 tiles:&nbsp; These are stored in exactly the
same way as 16x16 sprites; that is, the first and second rows have 14 ignored
tiles between them.&nbsp; (At least that's how it works when in 16-color
mode; I haven't figured out if it's the same for 4 or 256 colors but it's
very likely.)

<P>For more information on the tile map format, see <A HREF="#BGBasics">BG
Basics</A>.

<P><A NAME="Reg210B"></A><B><FONT FACE="Lucida Console">Register $210B/$210C:
Character location (2*1B/W)</FONT></B>
<PRE>$210B(low) $210C(high)&nbsp; a: BG1 address&nbsp; c: BG3 address
bbbbaaaa&nbsp;&nbsp; ddddcccc&nbsp;&nbsp;&nbsp;&nbsp; b: BG2 address&nbsp; d: BG4 address</PRE>
This register selects the location in VRAM where the tile map starts.&nbsp;
The byte address is calculated by shifting the four bits left by 13 (multiplying
by 8192).&nbsp; Note that, since there is only 64K of VRAM, the highest
of the four bits must be set to 0.

<P>For more information on storing characters, see <A HREF="#GraphicsFormat">The
SNES Graphics Format</A>.

<P><A NAME="Reg2115"></A><B><FONT FACE="Lucida Console">Register $2115:
Video Port Control (1b/W)</FONT></B>
<PRE>i---ffrr&nbsp; i: 0=increment when $2118 or $2139 is accessed
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1=increment when $2119 or $213A is accessed
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; f: full graphic (?)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; r: increment rate:&nbsp; 00=Increment by 2 bytes&nbsp;&nbsp; (1x1)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 01=Increment by 64 bytes&nbsp; (32x32)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 10=Increment by 128 bytes (64x64)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 11=Increment by 256 bytes (128x128)</PRE>
This register controls the way data is uploaded to VRAM.&nbsp; The bits
in here are a bit weird, but can be useful.&nbsp; When you want to change
only the high byte of a series of VRAM locations (register $2116 * 2 +
1), you should set i to 1.&nbsp; When you want to change just the low byte,
set i to 0.&nbsp; When you want to write a whole word, you should set i
to 0; otherwise, if i=1, writing a word will cause the high byte of the
first location to be changed, followed by the low byte of the next location.

<P>The r bits control the number of bytes by which the VRAM address pointer
gets incremented upon a read or write (see table.)

<P><A NAME="Reg2116"></A><B><FONT FACE="Lucida Console">Register $2116/$2117:
VRAM Address (2b/W)</FONT></B>
<PRE>aaaaaaaa aaaaaaaa&nbsp; a: word address for accessing VRAM</PRE>
This register is used to set the initial address for a VRAM upload or download.&nbsp;
Multiply by two to get the byte address.&nbsp; Note that, since there is
only 64K of VRAM, the most significant bit must be set to 0 (If the MSB
is set, it must be ignored.)

<P>When reading from VRAM, a "dummy read" must be performed after writing
to this register; the first value read is supposed to be meaningless.&nbsp;
No "dummy write" is required, however.

<P><A NAME="Reg2118"></A><B><FONT FACE="Lucida Console">Register $2118/$2119:
VRAM data write (2b/W)</FONT></B>
<PRE>dddddddd dddddddd&nbsp; d: data to write to VRAM</PRE>
When written, this register writes a byte or word to VRAM.&nbsp; The address
is incremented (or not, as the case may be) according to <A HREF="#Reg2115">register
$2115</A>.

<P><A NAME="Reg2139"></A><B><FONT FACE="Lucida Console">Register $2139/$213A:
VRAM data read (2b/R)</FONT></B>
<PRE>dddddddd dddddddd&nbsp; d: data read from VRAM</PRE>
When read from, this register downloads a byte or word from VRAM.&nbsp;
The address is incremented according to the settings of <A HREF="#Reg2115">register
$2115</A>.
<CENTER>&nbsp;</CENTER>

<CENTER><A NAME="RegVideo"></A><FONT SIZE=+2>Video Control Registers</FONT></CENTER>


<P><A NAME="Reg2100"></A><B><FONT FACE="Lucida Console">Register $2100:
Screen display register (1b/W)</FONT></B>
<PRE>d---bbbb&nbsp; d: disable screen (if 1, nothing should be displayed?)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; b: brightness. (0=almost black, 15=normal brightness)</PRE>
This register is used for screen fades.

<P><A NAME="Reg2105"></A><B><FONT FACE="Lucida Console">Register $2105:
Screen mode register (1b/W)</FONT></B>
<PRE>dcbapmmm&nbsp; d: BG4 tile size&nbsp; c: BG3 tile size&nbsp; b: BG2 tile size
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a: BG1 tile size&nbsp; Sizes are: 0=8x8; 1=16x16. (See <A HREF="#Reg2107">reg. $2107</A>)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; p: order of BG priorities&nbsp; m: General screen mode</PRE>
This register determines the size of tile represented by one entry in the
tile map array, the order that BGs are drawn on the screen, and the screen
mode.&nbsp; The screen modes are:
<PRE>MODE&nbsp;&nbsp; # of BGs&nbsp; Max Colors/Tile&nbsp;&nbsp; Palettes&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Colors Total
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 32 (8 per BG)&nbsp; 128 (32 per BG*4 BGs)
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1/BG2:16 BG3:4&nbsp; 8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1/BG2:128 BG3:32
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 16&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 128
3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1:256 BG2:16&nbsp;&nbsp;&nbsp; BG1:1 BG2:8&nbsp;&nbsp;&nbsp; BG1:256 BG2:128
4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1:256 BG2:4&nbsp;&nbsp;&nbsp;&nbsp; BG1:1 BG2:8&nbsp;&nbsp;&nbsp; BG1:256 BG2:32
5&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1:16 BG2:4&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1:128 BG2:32 (Interlaced mode)
6&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 16&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 128 (Interlaced mode)
7&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 256</PRE>
Notice that Mode 7 has only one BG.&nbsp; All games which appear to have
a Mode 7 screen but more than one BG either use sprites to simulate a BG,
or switch video modes midframe via HDMA.

<P>The p (priority bit) affects the order in which BGs are drawn on the
screen, as follows ("o" refers to the setting of bit 13 of the <A HREF="#BGBasics">tile
map</A>):
<PRE>p (Priority) 0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1
Drawn first&nbsp; BG4, o=0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG4, o=0
&nbsp;&nbsp; (Behind)&nbsp; BG3, o=0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG3, o=0
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sprites with OAM priority 0 (%00)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG4, o=1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG4, o=1
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG3, o=1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OAM pri. 1
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OAM pri. 1&nbsp;&nbsp;&nbsp; BG2, o=0
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG2, o=0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1, o=0
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1, o=0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG2, o=1
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Sprites with OAM priority 2 (%10)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; .&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG2, o=1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BG1, o=1
Drawn last&nbsp;&nbsp; BG1, o=1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; OAM pri. 3
&nbsp; (in front) OAM pri. 3&nbsp;&nbsp;&nbsp; BG3, o=1</PRE>
The p bit only works in Mode 1.&nbsp; In all other modes, it is ignored
(drawing is performed as if this bit were clear.)

<P><A NAME="Reg210D"></A><B><FONT FACE="Lucida Console">Register $210D
to $2114: Scroll Registers (Db/W)</FONT></B>
<PRE>210D: BG1 Horizontal Scroll&nbsp;&nbsp; 210E: BG1 Vertical Scroll
210F: BG2 Horizontal Scroll&nbsp;&nbsp; 2110: BG2 Vertical Scroll
2111: BG3 Horizontal Scroll&nbsp;&nbsp; 2112: BG3 Vertical Scroll
2113: BG4 Horizontal Scroll&nbsp;&nbsp; 2114: BG4 Vertical Scroll

mmmmmaaa aaaaaaaa&nbsp; a: Horizontal/Vertical offset m: Mode 7 only</PRE>
This register must be written twice to write the complete value; every
time the register is written to, an internal pointer alternates between
changing the high and low bytes.&nbsp; The first time you write to the
register, the low byte will be changed.&nbsp; There are 11 bits for the
offset; when these bits are set to 0, you will see tile map location 0
on the left/top of the screen.&nbsp; The offset is a pixel value, so adding
one will scroll the screen right by one pixel.&nbsp; When the screen is
scrolled right (or down) from 0, the rightmost (or bottommost) elements
of the tile map will come on from the left (top) of the screen.

<P>If a pixel value is placed in this register that is larger than the
width of the BG, a modulus can be performed to determine what the actual
pixel will be that is displayed.&nbsp; For example, if the BG1 horizontal
pixel value is set to 257, but the width of the BG is 256 pixels, the result
will be the same as if it was set to 1.

<P>The m bits are used in Mode 7 only; I don't know what they are for.&nbsp;
The only thing I've determined is that the scroll register seems to cause
pixel-based scrolling: that is, increasing this register by one will make
the screen scroll a slight amount right or down.&nbsp; (256/224 would be
one screenful.)

<P>Since there is only one BG in Mode 7, the 'm' bits apply only to registers
$210D and $210E.

<P><A NAME="Reg212C"></A><B><FONT FACE="Lucida Console">Register $212C
&amp; $212D: Main/Sub Screen Designation (2*1b/W)</FONT></B>
<PRE>210D: Main Screen Designation
210F: Sub Screen Designation

---sdcba&nbsp; s: sprites enable&nbsp; d: BG4 enable&nbsp; c: BG3 enable
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; b: BG2 enable&nbsp; a: BG1 enable</PRE>
The main screen designation is a way to toggle the BGs through software.&nbsp;
I think the Sub Screen designation has something to do with color add/subtract.

<P>&nbsp;
<CENTER><A NAME="RegWindows"></A><FONT SIZE=+2>Windowing Registers</FONT></CENTER>


<P>The SNES' Windowing registers are used for clipping; that is, cutting
off portions of the screen.&nbsp; If you run Mario World, you'll notice
a "circular opening" on the opening screen.&nbsp; This is done using windowing,
which clips off the parts of the screen outside of the window.&nbsp; The
clipping is only applied to BG1, BG2 and sprites, so that the big letters
"Mario World" (BG3) are always visible.&nbsp; Windowing has only a left
and right value, so what Mario World and many other games do is constantly
vary the left and right values using HDMA.

<P><A NAME="Reg2123"></A><B><FONT FACE="Lucida Console">Register $2123/$2124:
Window mask settings (2*1b/W)</FONT></B>

<P><TT>High Byte Low Byte&nbsp; 4: Settings for BG4&nbsp; 3: Settings for
BG3</TT>
<BR><TT>44443333&nbsp; 22221111&nbsp; 2: Settings for BG2&nbsp; 1: Settings
for BG1</TT>

<P><TT>Each BG has four bits, which have the following meanings:</TT>
<BR><TT>dcba&nbsp;&nbsp;&nbsp; d: Enable Window 2&nbsp; c: Clip Window
2 in or out&nbsp; (0=in,</TT>
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; b: Enable Window 1&nbsp;
a: Clip Window 1 in or out&nbsp;&nbsp; 1=out)</TT>

<P>These registers determine which Windows to apply to which BGs, and whether
clipping should be performed inside or outside the window.&nbsp; To enable