cpu.hpp

SNES game emulator. C and asm files.

#define REG210D(index) ((byte*)(registers + 0x010D + index))
	// Scroll registers & associated values--horizontal,vertical BG1; h,v BG2 etc
	// 8 double-write registers: first byte is low 8 bits, last byte b0-2:high 3 bits
	// (set to 0 except in mode 7) b3-7:mode 7 only
#define REG2115 ((byte*)(registers + 0x0115))
	// Video port control (VRAM upload settings control) b7:1=inc at 2119
#define REG2116 ((word*)(registers + 0x0116))
	// VRAM address register - write word
#define REG2118 ((word*)(registers + 0x0118))
	// VRAM write data 
#define REG2139 ((word*)(registers + 0x0139)) /*read-only*/
	// VRAM read data

/*MODE 7 REGISTERS*********************************************************/
#define REG211A ((byte*)(registers + 0x011A))
	// Mode 7 settings register
#define REG211B ((byte*)(registers + 0x011B))
#define REG211C ((byte*)(registers + 0x011C))
	// COS/SIN rotate angle/X expansion, $211B=16bit mult, $211C=8bit mult
#define REG211D ((byte*)(registers + 0x011D))
#define REG211E ((byte*)(registers + 0x011E))
	// SIN/COS rotate angle/Y expansion
#define REG211F ((byte*)(registers + 0x011F))
#define REG2120 ((byte*)(registers + 0x0120))
	// Center position X/Y (word) and associated values
#define REG2134 ((dword*)(registers + 0x0134)) /*read-only*/
	// 24-bit register--Mode 7 multiplication result

/*CGRAM (Palette) REGISTERS************************************************/
#define REG2121 ((byte*)(registers + 0x0121))
	// Palette (color #) selection register
#define REG2122 ((byte*)(registers + 0x0122))
	// Palette data write register
#define REG213B ((byte*)(registers + 0x013B)) /*read-only*/
	// Palette data read register

/*WINDOW REGISTERS*********************************************************/
#define REG2123 ((byte*)(registers + 0x0123))
	// Window mask settings register (BG2,BG1)
#define REG2124 ((byte*)(registers + 0x0124))
	// Window mask settings register (BG4,BG3)
#define REG2125 ((byte*)(registers + 0x0125))
	// Window mask settings register (Color,OBJ)
#define REG2126 ((byte*)(registers + 0x0126))
	// Window 1 left position
#define REG2127 ((byte*)(registers + 0x0127))
	// Window 1 right position
#define REG2128 ((byte*)(registers + 0x0128))
	// Window 2 left position
#define REG2129 ((byte*)(registers + 0x0129))
	// Window 2 right position
#define REG212A ((byte*)(registers + 0x012A))
	// Mask logic settings for BGs
#define REG212B ((byte*)(registers + 0x012B))
	// Mask logic settings for OBJs and Color windows

/*MORE VIDEO STUFF/COLOR ADD&SUB*******************************************/
#define REG212C ((byte*)(registers + 0x012C))
	// Main screen designation b0-4 Enable BGs/OAMs (b0=BG0, b4=sprites)
#define REG212D ((byte*)(registers + 0x012D))
	// Sub-screen designation b0-4 Enable BGs/OAMs (b0=BG0, b4=sprites)
#define REG212E ((byte*)(registers + 0x012E))
	// Window mask main screen designation
	// I'm guessing this must have a bit set to enable windows for that BG?
#define REG212F ((byte*)(registers + 0x012F))
	// Window mask sub screen designation
#define REG2130 ((byte*)(registers + 0x0130))
	// Fixed color add/subtraction register
#define REG2131 ((byte*)(registers + 0x0131))
	// in struct: byte reg2131setting [6];
	// Addition or subtraction select, etc and associated values
#define REG2132 ((byte*)(registers + 0x0132))
	// Fixed color add/sub data
#define REG2133 ((byte*)(registers + 0x0133))
inline int scans_before_vbl () {
	return (*REG2133 & 0x8) ? 239 : 224;
}
	// Screen mode b0:interlace b1:1=repeat OBJ dots(full height)
	// b2:0=224/1=239 lines b3:pseudo 512line mode b6:extbg(screen expand) b7:superimpose
#define REG2134 ((dword*)(registers + 0x0134)) /*read-only 24-bit*/
#define REG213E ((byte*)(registers + 0x013E)) /*read-only*/
	// PPU status flag/version number b7:time over b6:range over b5:master/slave b3-0:version
#define REG213F ((byte*)(registers + 0x013F)) /*read-only*/
	// PPU status flag/version number b7:field# in int.mode b6:ext.signal b4:1=PAL b0-3:version

/*MISC. REGISTERS**********************************************************/
#define REG2140 ((dword*)(registers + 0x0140)) /*read/write trapped*/
	// SPC700 communication ports
#define REG2180 ((byte*)(registers + 0x0180))
	// WRAM data - auto-increment
#define REG2181 ((dword*)(registers + 0x0181))
	// 24-bit WRAM address

/*COUNTER/TIMER REGISTERS**************************************************/
#define REG2137 ((byte*)(registers + 0x0137)) /*read-only*/
	// Sotware latch for horizontal/vertical counter, sets hcounter and vcounter.
#define REG213C ((byte*)(registers + 0x013C)) /*read-only? set by 2137*/
	//in struct boolean hhipointer;
	//word hcounter;
	// Horizontal scanline location and associated values
#define REG213D ((byte*)(registers + 0x013D)) /*read-only? set by 2137*/
	//boolean vhipointer;
	//word vcounter;
	// Vertical scanline location and associated values
#define REG4200 ((byte*)(registers + 0x2200)) /*read/write??*/
	// Counter enable b7:NMI interrupt b5:vertical IRQ b4:Horizontal IRQ b0:auto-read enable
	// if joypad is automatically read you can get the value from $4218 etc.
#define REG4207 ((word*)(registers + 0x2207))
	// Horizontal IRQ apply time (0-339;256-339 is overscan)
#define REG4209 ((word*)(registers + 0x2209))
	// Vertical IRQ apply time (o-261;224/239-261 is vblank)
#define REG4210 ((byte*)(registers + 0x2210))
	// This register gets read by the NMI handler to 'clear' the interrupt (i.e. turn off the
	// NMI request in the circuitry.) returns b7=1 when read, then b7=0 when it's read again. (?)
	// b0-3=version number
#define REG4211 ((byte*)(registers + 0x2211))
	// This register gets read by the IRQ handler to 'clear' the interrupt (i.e. turn off the
	// IRQ request in the circuitry.) returns b7=1 when read, then b7=0 when it's read again. (?)
#define REG4212 ((byte*)(registers + 0x2212))
	// Status register. b7=whether in VBlank b6=Whether in HBlank D0=joypad is ready to read?

/*MISC AND MATH REGISTERS**************************************************/
#define REG4201 ((byte*)(registers + 0x2201))
	// Programmable I/O Port output
#define REG4202 ((byte*)(registers + 0x2202))
	// Multiplicand 'A'--8-bit (A is set first)
#define REG4203 ((byte*)(registers + 0x2203))
	// Multiplier 'B'--8-bit (B is set last)
#define REG4204 ((word*)(registers + 0x2204))
	// Dividend 'C'--16-bit
#define REG4206 ((byte*)(registers + 0x2206))
	// Divisor-'B'--8-bit
#define REG420D ((byte*)(registers + 0x220D))
	// Cycle speed b0:FastROM
#define REG4213 ((byte*)(registers + 0x2213))
	// Programmable I/O Port (input)
#define REG4214 ((word*)(registers + 0x2214))
	// 16-bit quotient
#define REG4216 ((word*)(registers + 0x2216))
	// 16-bit multiplication result, or remainder

/*JOYPAD READING REGISTERS*************************************************/
#define REG4218(joypad) ((word*)(registers + 0x2218 + joypad*2))
	// Joypad status registers: low byte: b7=A b6=X b5=L button b4=R button;
	// high byte: b7=B b6=Y b5=Select b4=Start b3=Up b2=Down b1=Left b0=Right
	// 4218=Joypad 1 421A=Joypad 2 421C=Joypad 3 421E=Joypad 4
#define REG4016 ((byte*)(registers + 0x2016))
	// Old-style joypad. When read: b0:Data for controller 1 b1:Data for controller 2
	// When written:??? (Trigger strobe?) (17th bit returns whether joypad is connected)
#define REG4017 ((byte*)(registers + 0x2017))
	// b0:Data for controller 3 b1:data for controller 4??
#define REG420B ((byte*)(registers + 0x220B))
	// Set bits to initiate DMA transfer
#define REG420C ((byte*)(registers + 0x220C))
	// Same as $420B, but to enable automatic HDMA transfers
#define REG4300(chan) ((byte*)(registers + 0x2300 + (chan << 4)))
	// DMA Control Register b7:(DMA)0=CPU->PPU b6:(HDMA)0=Absolute 1=Indirect addressing
	// b4:0=Inc/Dec Addresses 1=Fixed Address b3:0=Increment 1=Decrement b0-2:transfer mode

#define REG4301(chan) ((byte*)(registers + 0x2301 + (chan << 4)))
	// $21xx address
#define REG4302(chan) ((dword*)(registers + 0x2302 + (chan << 4)))
	// 24-bit CPU address
#define REG4305(chan) ((word*)(registers + 0x2305 + (chan << 4)))
	// Bytes to transfer (DMA) or some kind of 24-bit CPU address (HDMA)
#define REG4307(chan) ((byte*)(registers + 0x2307 + (chan << 4)))
#define REG4308(chan) ((word*)(registers + 0x2308 + (chan << 4)))
#define REG430A(chan) ((byte*)(registers + 0x230A + (chan << 4)))
	// don't know what 4307+ are for
#define REG ((byte*)(registers + 0x))

#pragma pack (push,4)
extern "C" {
	extern struct ppuinternalregisters {  /* DO NOT CHANGE ORDER OF DATA! */
		boolean end_wai, within_wai; // flags to control WAI command behavior
		byte reg4210, reg4211;
		word scrollreg[8];
		byte reg2131setting [6]; // 0-3 BGs, 4 OBJs, 5 back area
		word hcounter, vcounter;
		byte reg2101;
		int vramincrate;
		signed short reg211B; // Mode 7 multiply 16bit
		signed char reg211C;  // Mode 7 multiply 8bit
		byte hdma_inprogress;
		short m7var[6];
		int oampointer, colorpointer;
		int vrampointer;
		int oldjoybit[2]; // Bit # in old joypad regs ($4016/$4017), incrememted after read
		boolean dummyread2139; // true if dummy read required (before "real" read on SNES VRAM)
	} state;
}
#pragma pack(pop)