📄 tiles.asm
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; Bp1=*(LineAddress+1)
mov cl,[esi+1]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL1_4+ebx*4]
mov bl,0x0F
or eax,[BPL1_4+ecx]
; Bp2=*(LineAddress+16)
mov cl,[esi+16]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL2_4+ebx*4]
mov bl,0x0F
or eax,[BPL2_4+ecx]
; Bp3=*(LineAddress+17)
mov cl,[esi+17]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL3_4+ebx*4]
or eax,[BPL3_4+ecx]
mov [C_LABEL(TileCache4)+edi*8],eax
add esi,byte 2
mov [C_LABEL(TileCache4)+edi*8+4],ebp
inc edi
dec dh
jnz .4bpl_line_loop
add esi,byte 16
dec dword [esp]
jnz .4bpl_tile_loop
pop eax
%endif
%ifndef NO_RECACHE_8BPL
mov edi,[Tile_Recache_Set_Begin]
mov edx,[Tile_Recache_Set_End]
inc edx ; edx = (Tile_Recache_Set_End / 4) + 1
sub edx,edi ; Count of 8bpl tiles to recache
shl edi,3 ; index for tile cache (*8)
push edx
lea esi,[C_LABEL(VRAM)+edi*8] ; address in VRAM of first 8bpl tile to recache
.8bpl_tile_loop:
mov dh,8
.8bpl_line_loop:
mov cl,[C_LABEL(TileCache8)+edi*8]
; Bp0=*(LineAddress+0)
mov dl,[esi]
mov bl,0x0F
mov cl,0xF0
and cl,dl
and bl,dl
shr cl,2
mov ebp,[BPL0_8+ebx*4]
mov bl,0x0F
mov eax,[BPL0_8+ecx]
; Bp1=*(LineAddress+1)
mov cl,[esi+1]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL1_8+ebx*4]
mov bl,0x0F
or eax,[BPL1_8+ecx]
; Bp2=*(LineAddress+16)
mov cl,[esi+16]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL2_8+ebx*4]
mov bl,0x0F
or eax,[BPL2_8+ecx]
; Bp3=*(LineAddress+17)
mov cl,[esi+17]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL3_8+ebx*4]
mov bl,0x0F
or eax,[BPL3_8+ecx]
; Bp4=*(LineAddress+32)
mov cl,[esi+32]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL4_8+ebx*4]
mov bl,0x0F
or eax,[BPL4_8+ecx]
; Bp5=*(LineAddress+33)
mov cl,[esi+33]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL5_8+ebx*4]
mov bl,0x0F
or eax,[BPL5_8+ecx]
; Bp6=*(LineAddress+48)
mov cl,[esi+48]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL6_8+ebx*4]
mov bl,0x0F
or eax,[BPL6_8+ecx]
; Bp7=*(LineAddress+49)
mov cl,[esi+49]
and bl,cl
and cl,0xF0
shr cl,2
or ebp,[BPL7_8+ebx*4]
or eax,[BPL7_8+ecx]
mov [C_LABEL(TileCache8)+edi*8],eax
add esi,byte 2
mov [C_LABEL(TileCache8)+edi*8+4],ebp
inc edi
dec dh
jnz .8bpl_line_loop
add esi,byte 48
dec dword [esp]
jnz .8bpl_tile_loop
pop eax
%endif
pop esi
pop ebp
pop edx
pop ecx
pop ebx
pop eax
ret
%macro P8_Plot_8 1-2 0 ;Xflip,Add=0
and esi,0x3FF*64+8*7
add esi,[TilesetAddress]
%ifnidni %1,Xflip
Plot_2 0,4,0,4
Plot_2 1,5,1,5
Plot_2 2,6,2,6
Plot_2 3,7,3,7
%else
Plot_2 7,3,0,4
Plot_2 6,2,1,5
Plot_2 5,1,2,6
Plot_2 4,0,3,7
%endif
%endmacro
%macro P16_Plot_8 1-2 0 ;Xflip,Add=0
%ifnidni %1,Xflip
push esi
call PLOT8_8BplTile
pop esi
add esi,byte 64
add edi,byte 8
call PLOT8_8BplTile
sub edi,byte 8
%else
push esi
add esi,byte 64
call PLOT8_8BplTile_X
pop esi
add edi,byte 8
call PLOT8_8BplTile_X
sub edi,byte 8
%endif
%endmacro
%macro P8_Plot_4 1-2 0 ;Xflip,Add=0
and esi,0x3FF*64+8*7
add esi,[TilesetAddress]
%ifnidni %1,Xflip
Plot_2_Paletted 0,4,0+%2,4+%2
Plot_2_Paletted 1,5,1+%2,5+%2
Plot_2_Paletted 2,6,2+%2,6+%2
Plot_2_Paletted 3,7,3+%2,7+%2
%else
Plot_2_Paletted 7,3,0+%2,4+%2
Plot_2_Paletted 6,2,1+%2,5+%2
Plot_2_Paletted 5,1,2+%2,6+%2
Plot_2_Paletted 4,0,3+%2,7+%2
%endif
%endmacro
%macro P8_Plot_Half_4 1-2 0 ;Xflip,Add=0
and esi,0x3FF*64+8*7
add esi,[TilesetAddress]
%ifnidni %1,Xflip
Plot_2_Paletted 0,4,0,2
Plot_2_Paletted 2,6,1,3
%else
Plot_2_Paletted 6,2,0,2
Plot_2_Paletted 4,0,1,3
%endif
%endmacro
%macro P16_Plot_Half_4 1-2 0 ;Xflip,Add=0
%ifnidni %1,Xflip
push esi
call PLOT8_4BplTile_Even
pop esi
add esi,byte 64
add edi,byte 4
call PLOT8_4BplTile_Even
sub edi,byte 4
%else
push esi
add esi,byte 64
call PLOT8_4BplTile_Even_X
pop esi
add edi,byte 4
call PLOT8_4BplTile_Even_X
sub edi,byte 4
%endif
%endmacro
%macro P16_Plot_4 1-2 0 ;Xflip,Add=0
%ifnidni %1,Xflip
push esi
call PLOT8_4BplTile
pop esi
add esi,byte 64
add edi,byte 8
call PLOT8_4BplTile
sub edi,byte 8
%else
push esi
add esi,byte 64
call PLOT8_4BplTile_X
pop esi
add edi,byte 8
call PLOT8_4BplTile_X
sub edi,byte 8
%endif
%endmacro
%macro P8_Plot_2 1-2 0 ;Xflip,Add=0
P8_Plot_4 %1,%2
%endmacro
%macro P8_Plot_Half_2 1-2 0 ;Xflip,Add=0
P8_Plot_Half_4 %1,%2
%endmacro
%macro P16_Plot_Half_2 1-2 0 ;Xflip,Add=0
%ifnidni %1,Xflip
push esi
call PLOT8_2BplTile_Even
pop esi
add esi,byte 64
add edi,byte 4
call PLOT8_2BplTile_Even
sub edi,byte 4
%else
push esi
add esi,byte 64
call PLOT8_2BplTile_Even_X
pop esi
add edi,byte 4
call PLOT8_2BplTile_Even_X
sub edi,byte 4
%endif
%endmacro
%macro P16_Plot_2 1-2 0 ;Xflip,Add=0
%ifnidni %1,Xflip
push esi
call PLOT8_2BplTile
pop esi
add esi,byte 64
add edi,byte 8
call PLOT8_2BplTile
sub edi,byte 8
%else
push esi
add esi,byte 64
call PLOT8_2BplTile_X
pop esi
add edi,byte 8
call PLOT8_2BplTile_X
sub edi,byte 8
%endif
%endmacro
EXPORT_C tile_plotters_text_start
ALIGNC
PLOT8_8BplTile:
P8_Plot_8 noflip
ret
ALIGNC
PLOT8_8BplTile_X:
P8_Plot_8 Xflip
ret
ALIGNC
PLOT8_4BplTile:
P8_Plot_4 noflip
ret
ALIGNC
PLOT8_4BplTile_X:
P8_Plot_4 Xflip
ret
ALIGNC
PLOT8_2BplTile:
P8_Plot_2 noflip
ret
ALIGNC
PLOT8_2BplTile_X:
P8_Plot_2 Xflip
ret
PLOT8_4BplTile_Even:
P8_Plot_Half_4 noflip
ret
PLOT8_4BplTile_Even_X:
P8_Plot_Half_4 Xflip
ret
PLOT8_2BplTile_Even:
P8_Plot_Half_2 noflip
ret
PLOT8_2BplTile_Even_X:
P8_Plot_Half_2 Xflip
ret
ALIGNC
PLOT16_4BplTile_Even:
P16_Plot_Half_4 noflip
ret
ALIGNC
PLOT16_4BplTile_Even_X:
P16_Plot_Half_4 Xflip
ret
ALIGNC
PLOT16_2BplTile_Even:
P16_Plot_Half_2 noflip
ret
ALIGNC
PLOT16_2BplTile_Even_X:
P16_Plot_Half_2 Xflip
ret
ALIGNC
PLOT16_8BplTile:
P16_Plot_8 noflip
ret
ALIGNC
PLOT16_8BplTile_X:
P16_Plot_8 Xflip
ret
ALIGNC
PLOT16_4BplTile:
P16_Plot_4 noflip
ret
ALIGNC
PLOT16_4BplTile_X:
P16_Plot_4 Xflip
ret
ALIGNC
PLOT16_2BplTile:
P16_Plot_2 noflip
ret
ALIGNC
PLOT16_2BplTile_X:
P16_Plot_2 Xflip
ret
ALIGNC
EXPORT Invalidate_Tile_Caches
mov dword [Tile_Recache_Set_Begin],0
mov dword [Tile_Recache_Set_End],0x3FF
ret
section .text
ALIGNC
section .data
ALIGND
section .bss
ALIGNB
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