ths8200_beta.c

DM642上用的TH8200采集芯片的配套驱动

		status &= I2C_writeReg(Devid,0x2A,0xC0); // dtg_spec_e 
		status &= I2C_writeReg(Devid,0x2B,0x01); // dtg_spec_h_msb 
		status &= I2C_writeReg(Devid,0x2C,0x90); // dtg_spec_h_lsb 
		status &= I2C_writeReg(Devid,0x2D,0x03); // dtg_spec_i_msb 
		status &= I2C_writeReg(Devid,0x2E,0x1B); // dtg_spec_i_lsb 
		status &= I2C_writeReg(Devid,0x2F,0x10); // dtg_spec_k_lsb 
		status &= I2C_writeReg(Devid,0x30,0x00); // dtg_spec_k_msb 
		status &= I2C_writeReg(Devid,0x31,0x00); // dtg_spec_k1 
		status &= I2C_writeReg(Devid,0x32,0xAD); // dtg_speg_g_lsb 
		status &= I2C_writeReg(Devid,0x33,0x01); // dtg_speg_g_msb 
		status &= I2C_writeReg(Devid,0x34,0x03); // dtg_total_pixel_msb 
		status &= I2C_writeReg(Devid,0x35,0x5A); // dtg_total_pixel_lsb 
		status &= I2C_writeReg(Devid,0x36,0x00); // dtg_linecnt_msb 
		status &= I2C_writeReg(Devid,0x37,0x01); // dtg_linecnt_lsb 
		status &= I2C_writeReg(Devid,0x38,0x85); // dtg_mode select 525 line progressive format 
		status &= I2C_writeReg(Devid,0x39,0x27); // dtg_frame_field_msb 
		status &= I2C_writeReg(Devid,0x3A,0x0D); // dtg_frame_size_lsb 
		status &= I2C_writeReg(Devid,0x3B,0xFF); // dtg_field_size_lsb 
		status &= I2C_writeReg(Devid,0x79,0x00); // dtg_hs_in_dly_msb adjusts horizontal input delay 
		status &= I2C_writeReg(Devid,0x7A,0x38); // dtg_hs_in_dly_lsb 
		status &= I2C_writeReg(Devid,0x7B,0x00); // dtg_vs_in_dly_msb adjust vertical input delay 
		status &= I2C_writeReg(Devid,0x7C,0x04); // dtg_vs_in_dly_lsb 
	}

///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
// THS8200 720p, 20bit input, embedded input syncs, YCbCr input, YPbPr output    //
///////////////////////////////////////////////////////////////////////////////////

	if(params->outFmt == YPbPr_720P_HDTV) {    
	/*Configure the input SYNC signal,either embedded or dedicated */	
		if(params->inFmt == BT656_EMBEDDED_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl            
		   status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl       
		}
		else if(params->inFmt == BT656_EXTERNAL_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl       
		}
		else if(params->inFmt == YCx20_EXTERNAL_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x03); // dman_cntl       
		}
		else if(params->inFmt == YCx20_EMBEDDED_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x1b); // dman_cntl       
		}
		else { 
		   return(FALSE);
		}
	
	/*configure Dispaly Time Generator,Data Manager */
		status &= I2C_writeReg(Devid,0x03,0x01); // chip_ctl 
		status &= I2C_writeReg(Devid,0x1D,0xFF); // dtg_y_sync1 setup tri-level sync 
		status &= I2C_writeReg(Devid,0x1E,0x49); // dtg_y_sync2 
		status &= I2C_writeReg(Devid,0x1F,0xB6); // dtg_y_sync3 
		status &= I2C_writeReg(Devid,0x20,0xFF); // dtg_cbcr_sync1 
		status &= I2C_writeReg(Devid,0x21,0xFF); // dtg_cbcr_sync2 
		status &= I2C_writeReg(Devid,0x22,0xFF); // dtg_cbcr_sync3 
		status &= I2C_writeReg(Devid,0x23,0x13); // dtg_y_sync_upper 
		status &= I2C_writeReg(Devid,0x24,0x15); // dtg_cbcr_sync_upper 
		status &= I2C_writeReg(Devid,0x25,0x28); // dtg_spec_a use spec registers to set up horizontal timing 
		status &= I2C_writeReg(Devid,0x26,0x6E); // dtg_spec_b 
		status &= I2C_writeReg(Devid,0x27,0x28); // dtg_spec_c 
		status &= I2C_writeReg(Devid,0x28,0x04); // dtg_spec_d 
		status &= I2C_writeReg(Devid,0x2A,0x04); // dtg_spec_e 
		status &= I2C_writeReg(Devid,0x2B,0xC0); // dtg_spec_h_msb 
		status &= I2C_writeReg(Devid,0x2C,0x00); // dtg_spec_h_lsb 
		status &= I2C_writeReg(Devid,0x2F,0x6E); // dtg_spec_k_lsb 
		status &= I2C_writeReg(Devid,0x30,0x00); // dtg_spec_k_msb 
		status &= I2C_writeReg(Devid,0x34,0x06); // dtg_total_pixel_msb 1650 pixels per line 
		status &= I2C_writeReg(Devid,0x35,0x72); // dtg_total_pixel_lsb 
		status &= I2C_writeReg(Devid,0x36,0x00); // dtg_linecnt_msb 
		status &= I2C_writeReg(Devid,0x37,0x01); // dtg_linecnt_lsb 
		status &= I2C_writeReg(Devid,0x38,0x82); // dtg_mode select 720p mode (defines vertical structure the video frame) 
		status &= I2C_writeReg(Devid,0x39,0x27); // dtg_frame_field_msb 2EEh for 750 lines per frame 
		status &= I2C_writeReg(Devid,0x3A,0xEE); // dtg_frame_size_lsb 
		status &= I2C_writeReg(Devid,0x3B,0xFF); // dtg_field_size_lsb 
		status &= I2C_writeReg(Devid,0x79,0x00); // dtg_hs_in_dly_msb adjusts horizontal input delay 
		status &= I2C_writeReg(Devid,0x7A,0x60); // dtg_hs_in_dly_lsb 
		status &= I2C_writeReg(Devid,0x7B,0x00); // dtg_vs_in_dly_msb adjust vertical input delay 
		status &= I2C_writeReg(Devid,0x7C,0x07); // dtg_vs_in_dly_lsb 
	}

///////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////
// THS8200 1080i, 20bit input, embedded input syncs, YCbCr input, YPbPr output   //
///////////////////////////////////////////////////////////////////////////////////

	if(params->outFmt == YPbPr_1080i_HDTV) {    
	/*Configure the input SYNC signal,either embedded or dedicated */	
		if(params->inFmt == BT656_EMBEDDED_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl            
		   status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl       
		}
		else if(params->inFmt == BT656_EXTERNAL_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x04); // dman_cntl       
		}
		else if(params->inFmt == YCx20_EXTERNAL_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x1F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x03); // dman_cntl       
		}
		else if(params->inFmt == YCx20_EMBEDDED_SYNC) {
		   status &= I2C_writeReg(Devid,0x82,0x3F); // pol_cntl   
		   status &= I2C_writeReg(Devid,0x1C,0x03); // dman_cntl       
		}
		else { 
		   return(FALSE);
		}
	
		status &= I2C_writeReg(Devid,0x03,0x11); // chip_ctl 
		status &= I2C_writeReg(Devid,0x1D,0xFF); // dtg_y_sync1 setup tri-level sync 
		status &= I2C_writeReg(Devid,0x1E,0x49); // dtg_y_sync2 
		status &= I2C_writeReg(Devid,0x1F,0xB6); // dtg_y_sync3 
		status &= I2C_writeReg(Devid,0x20,0xFF); // dtg_cbcr_sync1 
		status &= I2C_writeReg(Devid,0x21,0xFF); // dtg_cbcr_sync2 
		status &= I2C_writeReg(Devid,0x22,0xFF); // dtg_cbcr_sync3 
		status &= I2C_writeReg(Devid,0x23,0x13); // dtg_y_sync_upper 
		status &= I2C_writeReg(Devid,0x24,0x15); // dtg_cbcr_sync_upper 
		status &= I2C_writeReg(Devid,0x25,0x2C); // dtg_spec_a use spec registers to set up horizontal timing 
		status &= I2C_writeReg(Devid,0x26,0x58); // dtg_spec_b 
		status &= I2C_writeReg(Devid,0x27,0x2C); // dtg_spec_c 
		status &= I2C_writeReg(Devid,0x28,0x84); // dtg_spec_d 
		status &= I2C_writeReg(Devid,0x2A,0xC0); // dtg_spec_e 
		status &= I2C_writeReg(Devid,0x2B,0x00); // dtg_spec_h_msb 
		status &= I2C_writeReg(Devid,0x2C,0x00); // dtg_spec_h_lsb 
		status &= I2C_writeReg(Devid,0x2F,0x58); // dtg_spec_k_lsb 
		status &= I2C_writeReg(Devid,0x30,0x00); // dtg_spec_k_msb 
		status &= I2C_writeReg(Devid,0x32,0x58); // dtg_speg_g_lsb 
		status &= I2C_writeReg(Devid,0x33,0x00); // dtg_speg_g_msb 
		status &= I2C_writeReg(Devid,0x34,0x08); // dtg_total_pixel_msb 
		status &= I2C_writeReg(Devid,0x35,0x98); // dtg_total_pixel_lsb 
		status &= I2C_writeReg(Devid,0x36,0x00); // dtg_linecnt_msb 
		status &= I2C_writeReg(Devid,0x37,0x01); // dtg_linecnt_lsb 
		status &= I2C_writeReg(Devid,0x38,0x81); // dtg_mode select 1080i mode (defines vertical structure the video frame) 
		status &= I2C_writeReg(Devid,0x39,0x42); // dtg_frame_field_msb 465h =1125 lines per frame 
		status &= I2C_writeReg(Devid,0x3A,0x65); // dtg_frame_size_lsb 233h = 563 lines per field 
		status &= I2C_writeReg(Devid,0x3B,0x33); // dtg_field_size_lsb 
		status &= I2C_writeReg(Devid,0x79,0x00); // dtg_hs_in_dly_msb adjusts horizontal input delay 
		status &= I2C_writeReg(Devid,0x7A,0x44); // dtg_hs_in_dly_lsb 
		status &= I2C_writeReg(Devid,0x7B,0x00); // dtg_vs_in_dly_msb adjust vertical input delay 
		status &= I2C_writeReg(Devid,0x7C,0x01); // dtg_vs_in_dly_lsb 
	}                                     
  	                                      
  	if(!status)
		return(FALSE);
	else
		return(TRUE);
}






static Int THS8200_ctrl(EDC_Handle handle, unsigned int cmd, Arg arg1){
	Bool status = FALSE;
	int Devid = (int)handle;
	/*First Check if the Handle is correct */
	if(Devid == THS8200_address || Devid == THS8200_address+2) {
	    switch(cmd) {
			case EDC_CONFIG:
			status = THS8200_config(handle, (void *)arg1);
			break;
			default:
			break;
    	}
    }
    return status;

}
static Int THS8200_close(EDC_Handle handle) {
	int status = 1;
	int Devid = (int)handle;
	/*First Check if the Handle is correct */
	if(Devid != THS8200_address && Devid != THS8200_address+2)
	   return(FALSE);
	/*Put THS8200 in power down mode,all dac and digital logic except I2C */
	status &= I2C_writeReg(Devid,0x03,0x0C);
	if(!status)
		return(FALSE);
	else
		return(TRUE);
}	        

static EDC_Handle THS8200_open(char* devName, Arg optArg) {
	
	int DevId = THS8200_address;
    	/* Reset all the functional block */
//#ifdef THS8200_BUG
//		if(I2C_writeReg(DevId,0x03,0x01)){
//			return((EDC_Handle)(DevId));
//		}
//#else
	return((EDC_Handle)(DevId));
//#endif
//    return INV;
}

far EDC_Fxns EDC_THS8200_Fxns = {
    THS8200_open,
    THS8200_close,
    THS8200_ctrl
};