📄 求助：8路抢答器的vhdl实现（有问题，希望大家帮忙解决，谢谢）--综合电子论坛.mht
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<DIV style=3D"BACKGROUND: #fff; OVERFLOW: hidden; HEIGHT: 1px"></DIV>
<DIV style=3D"MARGIN: 10px">
<DIV=20
style=3D"MARGIN-TOP: 10px; FONT-SIZE: 9pt; MIN-HEIGHT: 160px; =
WORD-BREAK: break-all; LINE-HEIGHT: normal; HEIGHT: auto! important; =
WORD-WRAP: break-word">
<DIV style=3D"LINE-HEIGHT: 22px; HEIGHT: 22px"><IMG alt=3D=B1=ED=C7=E9=20
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align=3DabsMiddle><STRONG></STRONG></DIV>3=B5=B9=BC=C6=CA=B1=A3=A8=D3=C3=D3=
=DA=BF=D8=D6=C6=C7=C0=B4=F0=B5=C4=CA=B1=BC=E4=A3=A9<BR>library ieee =
;<BR>use=20
ieee.std_logic_1164.all;<BR>use ieee.std_logic_arith.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR><BR>entity deliver is=20
<BR>port( data:in std_logic_vector(3 =
downto=20
0);<BR> =
load:in=20
std_logic;<BR>  =
; clk:in=20
std_logic;<BR>  =
;=20
down:in std_logic;<BR> temp_data:in=20
std_logic_vector(3 downto 0);<BR> =20
data_out:out std_logic_vector(3 downto 0));<BR>end =
deliver;<BR><BR>architecture=20
del of deliver=20
is<BR>begin<BR>process(clk,load,down)<BR>begin<BR>  =
; if=20
clk=A3=A7event and clk=3D=A3=A71=A3=A7 =
then<BR> if=20
load=3D=A3=A71=A3=A7 then=20
data_out<=3Ddata;<BR> &=
nbsp; =20
elsif down=3D=A3=A71=A3=A7 then=20
data_out<=3Dtemp_data;<BR> &n=
bsp;end=20
if;<BR> end if;<BR>end process; =
<BR>end=20
del;<BR><BR><BR>library ieee ;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_arith.all;<BR><BR>entity over is <BR>port(data:in=20
std_logic_vector(3 downto 0);<BR> zero:out=20
std_logic);<BR>end over;<BR><BR>architecture ove of over=20
is<BR>begin<BR> zero<=3D=A3=A71=A3=A7 =
when(data=3D"0000")=20
else<BR> =
=A3=A70=A3=A7;<BR>end=20
ove;<BR><BR><BR>library ieee ;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_arith.all;<BR>use =
ieee.std_logic_unsigned.all;<BR><BR>entity=20
subtraction is <BR>port( data:in =
std_logic_vector(3=20
downto 0);<BR> temp_data:out std_logic_vector(3 =
downto=20
0));<BR>end subtraction;<BR><BR>architecture sub of subtraction =
is<BR>signal=20
temp:std_logic_vector(3 downto=20
0):=3Ddata;<BR>begin<BR> temp_data<=3D"1001" =
when=20
(unsigned (data)=3D0)=20
else<BR>  =
; unsigned=20
(data)-1;<BR>end sub;<BR><BR><BR>library ieee ;<BR>use=20
ieee.std_logic_1164.all;<BR><BR>entity bcd_7seg is<BR>port(bcd_led : in=20
std_logic_vector(3 downto =
0);<BR> ledseg :=20
out std_logic_vector(6 downto 0));<BR>end bcd_7seg;<BR><BR>architecture =
bcd of=20
bcd_7seg is <BR>begin <BR> with bcd_led=20
select<BR> ledseg<=3D"0111111" when=20
"0000",--0<BR>  =
; "0000110"=20
when=20
"0001",--1<BR>  =
; "1011011"=20
when=20
"0010",--2<BR>  =
; "1001111"=20
when=20
"0011",--3<BR>  =
; "1100110"=20
when=20
"0100",--4<BR>  =
; "1101101"=20
when=20
"0101",--5<BR>  =
; "1111101"=20
when=20
"0110",--6<BR>  =
; "0100111"=20
when=20
"0111",--7<BR>  =
; "1111111"=20
when=20
"1000",--8<BR>  =
; "1101111"=20
when=20
"1001",--9<BR>  =
; "0000000"=20
when others;<BR>end =
bcd;<BR><BR><BR>=D4=AA=BC=FE=C0=FD=BB=AF=D6=AE=BA=F3=A3=BA<BR>library =
ieee ;<BR>use=20
ieee.std_logic_1164.all;<BR>use ieee.std_logic_arith.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR><BR>entity count1 is=20
<BR>port( data:in std_logic_vector(3 =
downto=20
0);<BR> =
load:in=20
std_logic;<BR>  =
; clk:in=20
std_logic;<BR>  =
;=20
down:in std_logic;<BR> timeover:out=20
std_logic;<BR> timeout:out=
=20
std_logic_vector(6 downto 0));<BR>end count1;<BR><BR>architecture cou1 =
of count1=20
is<BR><BR>signal a,b:std_logic_vector(3 downto 0);<BR><BR>component =
deliver is=20
<BR>port( data:in std_logic_vector(3 =
downto=20
0);<BR> =
load:in=20
std_logic;<BR>  =
; clk:in=20
std_logic;<BR>  =
;=20
down:in std_logic;<BR> temp_data:in=20
std_logic_vector(3 downto 0);<BR> =20
data_out:out std_logic_vector(3 downto 0));<BR>end component=20
deliver;<BR><BR>component subtraction is =
<BR>port( =20
data:in std_logic_vector(3 downto 0);<BR> =
temp_data:out=20
std_logic_vector(3 downto 0));<BR>end component =
subtraction;<BR><BR>component=20
bcd_7seg is<BR>port(bcd_led : in std_logic_vector(3 downto=20
0);<BR> ledseg : out =
std_logic_vector(6=20
downto 0));<BR>end component bcd_7seg;<BR>component over is =
<BR>port(data:in=20
std_logic_vector(3 downto 0);<BR> zero:out=20
std_logic);<BR>end component over;<BR>begin<BR> u1: deliver =
port map=20
(data,load,clk,down,a,b);<BR> u2: subtraction port map=20
(b,a);<BR> u3: bcd_7seg port map =
(b,timeout);<BR> u4:=20
over port map (b,timeover);<BR>end =
cou1;<BR>=B5=C3=B5=BD=D2=BB=CE=BB=CA=FD=B5=C3=BC=F5=B7=A8=20
=A1=A3=A1=BF<BR><BR>=CF=C2=C3=E6=CA=C7=C1=BD=CE=BB=CA=FD=B5=C4=A3=BA<BR>l=
ibrary ieee ;<BR>use ieee.std_logic_1164.all;<BR>use=20
ieee.std_logic_unsigned.all;<BR><BR>entity count is=20
<BR>port( data:in std_logic_vector(7 =
downto=20
0);<BR> =
load:in=20
std_logic;<BR>  =
; clk:in=20
std_logic;<BR>  =
;=20
down:in std_logic;<BR> timeover:out=20
std_logic;<BR> timeout0:out=20
std_logic_vector(6 downto 0);<BR> =20
timeout1:out std_logic_vector(6 downto 0));<BR>end =
count;<BR>architecture cou of=20
count is<BR>component count1 is=20
<BR>port( data:in std_logic_vector(3 =
downto=20
0);<BR> =
load:in=20
std_logic;<BR>  =
; clk:in=20
std_logic;<BR>  =
;=20
down:in std_logic;<BR> timeover:out=20
std_logic;<BR> timeout:out=
=20
std_logic_vector(6 downto 0));<BR>end component count1;<BR>signal=20
data1,data0:std_logic_vector(3 downto 0);<BR>signal=20
timeover0,timeover1,down0,down1:std_logic;<BR>begin<BR> =20
data1<=3Ddata(7 downto 4);<BR> data0<=3Ddata(3 downto=20
0);<BR> process(timeover0,timeover1,down)<BR> =20
begin<BR> <BR> =
if=20
down=3D=A3=A71=A3=A7 then =
down0<=3D=A3=A71=A3=A7;down1<=3D=A3=A70=A3=A7;end=20
if;<BR><BR> if =
timeover0=3D=A3=A71=A3=A7 then=20
down1<=3D=A3=A71=A3=A7;=20
down0<=3D=A3=A71=A3=A7;<BR> &=
nbsp; elsif=20
timeover1=3D=A3=A71=A3=A7 then=20
down1<=3D=A3=A70=A3=A7;<BR> &=
nbsp; elsif=20
timeover0=3D=A3=A71=A3=A7and timeover1=3D=A3=A71=A3=A7 then=20
down1<=3D=A3=A70=A3=A7;down0<=3D=A3=A70=A3=A7;<BR>  =
; end=20
if;<BR><BR> timeover<=3D=
timeover0=20
and timeover1; <BR><BR>end=20
process; <BR><BR> &nb=
sp; =20
u1: count1 port map=20
(data1,load,clk,down1,timeover1,timeout1);--=B8=DF=CE=BB<BR> =
u0: count1 port=20
map (data0,load,clk,down0,timeover0,timeout0);--=B5=CD=CE=BB<BR>end =
cou;<BR><BR><BR></DIV>
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21:15:00</DIV>-----------------------------------------------------------=
----<BR>=D7=DB=BA=CF=B5=E7=D7=D3=C2=DB=CC=B3=BB=B6=D3=AD=C4=FA=A3=A1=20
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