error_routine.c

富士通单片机９０５４０ＣＡＮ总线通信源代码

/**    THIS SAMPLE CODE IS PROVIDED AS IS. FUJITSU MICROELECTRONICS     **/
/** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR OMMISSIONS **/
/*****************************************************************************
 *  Date   :        2002/11/01
 *  PROJECT:        error_routine
*****************************************************************************/
#include "_ffmc16.h"

error_judge_CAN0()
{
	int i;
	switch(IO_CANCT0.CSR.bit.NS )
		{
			case 0:
					IO_CANCT0.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P44 = 0;		/* error active */
					IO_PDR4.bit.P45 = 1;
					IO_PDR4.bit.P46 = 1;
					IO_PDR4.bit.P47 = 1;
					break;
			case 1:
					IO_CANCT0.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P44 = 0;		/* warning */
					IO_PDR4.bit.P45 = 0;
					IO_PDR4.bit.P46 = 1;
					IO_PDR4.bit.P47 = 1;
					break;
			case 2:
					IO_CANCT0.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P44 = 0;		/* error passive */
					IO_PDR4.bit.P45 = 0;
					IO_PDR4.bit.P46 = 0;
					IO_PDR4.bit.P47 = 1;
					break;
			default:
					IO_PDR4.bit.P44 = 0;		/* bus off */
					IO_PDR4.bit.P45 = 0;
					IO_PDR4.bit.P46 = 0;
					IO_PDR4.bit.P47 = 0;

					if(IO_CANCT0.CSR.bit.HALT == 1){
						/* CAN Bus start */
						IO_CANCT0.CSR.word = 0x0084;/* Control status register */
					}
					break;
		}
}
error_judge_CAN1()
{
	int j;
	switch(IO_CANCT1.CSR.bit.NS )
		{
			case 0:
					IO_CANCT1.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P40 = 0;		/* error active */
					IO_PDR4.bit.P41 = 1;
					IO_PDR4.bit.P42 = 1;
					IO_PDR4.bit.P43 = 1;
					break;
			case 1:
					IO_CANCT1.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P40 = 0;		/* warning */
					IO_PDR4.bit.P41 = 0;
					IO_PDR4.bit.P42 = 1;
					IO_PDR4.bit.P43 = 1;
					break;
			case 2:
					IO_CANCT1.CSR.bit.NT = 0;	/* NTbit clear */
					IO_PDR4.bit.P40 = 0;		/* error passive */
					IO_PDR4.bit.P41 = 0;
					IO_PDR4.bit.P42 = 0;
					IO_PDR4.bit.P43 = 1;
					break;
			default:
					IO_PDR4.bit.P40 = 0;		/* bus off */
					IO_PDR4.bit.P41 = 0;
					IO_PDR4.bit.P42 = 0;
					IO_PDR4.bit.P43 = 0;

					if(IO_CANCT1.CSR.bit.HALT == 1){
						/* CAN Bus start */
						IO_CANCT1.CSR.word = 0x0084;		/* Control status register */
					}
					break;
		}
}