📄 pocsag_decoder.lst
字号:
(0257) ;and initialize ClockNotStable, which can be used as a flag in _main to
(0258) ;indicate that the clocks are stable. It is also used as a state
(0259) ;variable for the clock initialization.
(0260)
(0261) M8C_SetBank1
(0262) mov reg[PRT1DM0],00h ;P1[0] & P1[1] Drive Mode to High Z because
(0263) mov reg[PRT1DM1],03h ; LoadConfigInit not run yet.
(0264) mov reg[ECO_TR],0Fh ;adjust ECO trim
(0265) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0266) ; set sleep to 1 sec and CPU to 12MHz during configuration
(0267) mov reg[OSC_CR0], (OSC_CR0_CPU_12MHz | OSC_CR0_Sleep_1Hz)
(0268) ELSE
(0269) ; set sleep to 1 sec and CPU to 24MHz
(0270) mov reg[OSC_CR0], (OSC_CR0_CPU_24MHz | OSC_CR0_Sleep_1Hz)
(0271) ENDIF
(0272) M8C_SetBank0
(0273)
(0274) M8C_ClearWDTAndSleep ;reset the sleep timer
(0275) M8C_SetBank1
(0276) or reg[OSC_CR0],SELECT_32K_JUST ;enable the ECO
(0277)
(0278) M8C_SetBank0
(0279) M8C_EnableIntMask INT_MSK0, INT_MSK0_Sleep
(0280) mov [ClockNotStable],FIRST_TIME ;initialize ClockNotStable
(0281) ELSE ; If 32K is set to Internal, then no further initialization needed
(0282) M8C_SetBank1
(0283) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0284) ; set sleep to 1 sec and CPU to 12MHz during configuration
(0285) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
(0286) ELSE
(0287) ; set sleep to 1 sec and CPU to 24MHz
(0288) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST )
0054: 62 E0 1B MOV REG[224],27
0057: 70 EF AND F,239
(0289) ENDIF
(0290) M8C_SetBank0
(0291) ENDIF
(0292)
(0293) ; default CT block RTopMux to OUT and RBotMux to AGND
(0294) mov reg[ACA00CR0],05h
0059: 62 71 05 MOV REG[113],5
(0295) mov reg[ACA01CR0],05h
005C: 62 75 05 MOV REG[117],5
(0296) mov reg[ACA02CR0],05h
005F: 62 79 05 MOV REG[121],5
(0297) mov reg[ACA03CR0],05h
0062: 62 7D 05 MOV REG[125],5
(0298) lcall LoadConfigInit ;Configure PSoC blocks per Dev Editor
0065: 7C 03 DF LCALL LoadConfigInit
(0299)
(0300) IF C_LANGUAGE_SUPPORT
(0301) call InitCRunTime ;Initialize for C language
0068: 90 08 CALL 0x0072
(0302) ENDIF
(0303) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0304) ; Set the CPU clock to the user's selection
(0305) M8C_SetBank1
(0306) mov reg[OSC_CR0], (SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
(0307) M8C_SetBank0
(0308) ENDIF
(0309)
(0310) mov reg[INT_VC],0 ;Clear any pending interrupts which may
006A: 62 E2 00 MOV REG[226],0
(0311) ; have been set during the boot process.
(0312) IF SELECT_32K
(0313) M8C_EnableGInt ;Enable global interrupts
(0314) ENDIF
(0315)
(0316) lcall _main ;Call main
006D: 7C 01 00 LCALL __text_start
(0317) _exit:
(0318) jmp _exit
0070: 8F FF JMP 0x0070
(0319)
(0320) IF C_LANGUAGE_SUPPORT
(0321) ;-----------------------------------------------------------------------------
(0322) ;; C Runtime Environment Initialization
(0323) ;-----------------------------------------------------------------------------
(0324)
(0325) InitCRunTime:
(0326) ;-----------------------------
(0327) ; clear bss segment
(0328) ;-----------------------------
(0329) mov A,0
0072: 50 00 MOV A,0
(0330) mov [__r0],<__bss_start
0074: 55 00 01 MOV [__r0],1
(0331) BssLoop:
(0332) cmp [__r0],<__bss_end
0077: 3C 00 0E CMP [__r0],14
(0333) jz BssDone
007A: A0 05 JZ 0x0080
(0334) mvi [__r0],A
007C: 3F 00 MVI [__r0],A
(0335) jmp BssLoop
007E: 8F F8 JMP 0x0077
(0336) BssDone:
(0337) ;----------------------------
(0338) ; copy idata to data segment
(0339) ;----------------------------
(0340) mov A,>__idata_start
0080: 50 01 MOV A,1
(0341) mov X,<__idata_start
0082: 57 00 MOV X,0
(0342) mov [__r0],<__data_start
0084: 55 00 00 MOV [__r0],0
(0343) IDataLoop:
(0344) cmp [__r0],<__data_end
0087: 3C 00 00 CMP [__r0],0
(0345) jz IDataDone
008A: A0 0B JZ 0x0096
(0346) push A
008C: 08 PUSH A
(0347) romx
008D: 28 ROMX
(0348) mvi [__r0],A
008E: 3F 00 MVI [__r0],A
(0349) pop A
0090: 18 POP A
(0350) inc X
0091: 75 INC X
(0351) adc A,0
0092: 09 00 ADC A,0
(0352) jmp IDataLoop
0094: 8F F2 JMP 0x0087
(0353) IDataDone:
(0354) ret
0096: 7F RET
0097: 30 HALT
0098: 30 HALT
0099: 30 HALT
009A: 30 HALT
009B: 30 HALT
009C: 30 HALT
009D: 30 HALT
009E: 30 HALT
009F: 30 HALT
00A0: 30 HALT
00A1: 30 HALT
00A2: 30 HALT
00A3: 30 HALT
00A4: 30 HALT
00A5: 30 HALT
00A6: 30 HALT
00A7: 30 HALT
00A8: 30 HALT
00A9: 30 HALT
00AA: 30 HALT
00AB: 30 HALT
00AC: 30 HALT
00AD: 30 HALT
00AE: 30 HALT
00AF: 30 HALT
00B0: 30 HALT
00B1: 30 HALT
00B2: 30 HALT
00B3: 30 HALT
00B4: 30 HALT
00B5: 30 HALT
00B6: 30 HALT
00B7: 30 HALT
00B8: 30 HALT
00B9: 30 HALT
00BA: 30 HALT
00BB: 30 HALT
00BC: 30 HALT
00BD: 30 HALT
00BE: 30 HALT
00BF: 30 HALT
00C0: 30 HALT
00C1: 30 HALT
00C2: 30 HALT
00C3: 30 HALT
00C4: 30 HALT
00C5: 30 HALT
00C6: 30 HALT
00C7: 30 HALT
00C8: 30 HALT
00C9: 30 HALT
00CA: 30 HALT
00CB: 30 HALT
00CC: 30 HALT
00CD: 30 HALT
00CE: 30 HALT
00CF: 30 HALT
00D0: 30 HALT
00D1: 30 HALT
00D2: 30 HALT
00D3: 30 HALT
00D4: 30 HALT
00D5: 30 HALT
00D6: 30 HALT
00D7: 30 HALT
00D8: 30 HALT
00D9: 30 HALT
00DA: 30 HALT
00DB: 30 HALT
00DC: 30 HALT
00DD: 30 HALT
00DE: 30 HALT
00DF: 30 HALT
00E0: 30 HALT
00E1: 30 HALT
00E2: 30 HALT
00E3: 30 HALT
00E4: 30 HALT
00E5: 30 HALT
00E6: 30 HALT
00E7: 30 HALT
00E8: 30 HALT
00E9: 30 HALT
00EA: 30 HALT
00EB: 30 HALT
00EC: 30 HALT
00ED: 30 HALT
00EE: 30 HALT
00EF: 30 HALT
00F0: 30 HALT
00F1: 30 HALT
00F2: 30 HALT
00F3: 30 HALT
00F4: 30 HALT
00F5: 30 HALT
00F6: 30 HALT
00F7: 30 HALT
00F8: 30 HALT
00F9: 30 HALT
00FA: 30 HALT
00FB: 30 HALT
00FC: 30 HALT
00FD: 30 HALT
00FE: 30 HALT
00FF: 30 HALT
FILE: C:\PROGRA~1\CYPRES~1\PSOCDE~1\PROJECTS\POCSAG~1\MAIN.ASM
(0001) ;-----------------------------------------------------------------------------
(0002) ; File : main.asm
(0003) ; Decs. : This file contains functions for POCSAG_Decoder project.
(0004) ; Operation : Search for POCSAG preambule, identify data bit rate, perform
(0005) ; synchronization to receiving packet, copy it into UART
(0006) ;-----------------------------------------------------------------------------
(0007) include "m8c.inc" ;include m8c specific declarations
(0008) include "cmpprg_1.inc" ;include CMPPRG_1 module specific declarations
(0009) include "timer8_1.inc" ;include Timer8_1 module specific declarations
(0010) include "tx8_1.inc" ;include TX8_1 module specific declarations
(0011) include "pga_1.inc" ;include PGA_1 module specific declarations
(0012)
(0013) export _main
(0014) export GPIO_ISR
(0015) export TIMER8_1_ISR
(0016) export COMP_ISR
(0017)
(0018) RATE_2400_HI: EQU 218 ;Upper margin for 2400 bps data rate
(0019) RATE_2400_LO: EQU 188 ;Lower margin for 2400 bps data rate
(0020) RATE_1200_HI: EQU 181 ;Upper margin for 1200 bps data rate
(0021) RATE_1200_LO: EQU 121 ;Lower margin for 1200 bps data rate
(0022) RATE_512_HI: EQU 71 ;Upper margin for 512 bps data rate
(0023) RATE_512_LO: EQU 1 ;Lower margin for 512 bps data rate
(0024) RATE_CHECK: EQU 255 ;Number of time to check data rate
(0025) SAMPLING_RATE_2400: EQU 5 ;6-1, Timer period for 2400 bps sampling
(0026) SAMPLING_RATE_1200: EQU 11 ;12-1, Timer period for 1200 bps sampling
(0027) SAMPLING_RATE_512: EQU 26 ;27-1, Timer period for 512 bps sampling
(0028) SAMPLE_NUM: EQU 9 ;Number of time to sample comparator output in one period
(0029) MSB_NUM: EQU 7 ;Number of bit shifts in one byte
(0030) BYTE_NUM: EQU 68 ;Number of bytes in one batch
(0031)
(0032) area bss(RAM) ;inform assembler that variables follow
(0033)
(0034) ready: blk 1 ;flag that GPIO interrupt is occured
(0035) start: blk 1 ;flag to disable GPIO and enable COMP interrupts
(0036) rate: blk 1 ;period of received data
(0037) bit_ptr: blk 1 ;pointer to bit position in the byte
(0038) hi_cnt: blk 1 ;counter of positive values
(0039) lo_cnt: blk 1 ;counter of negative values
(0040) data: blk 1 ;byte of combined received bits
(0041) byte_cnt: blk 1 ;counter of received bytes
(0042) sample_cnt: blk 1 ;counter of comparator sampling times
(0043) sampling_rate: blk 1 ;timer period for comparator sampling
(0044) saved_bit: blk 1 ;previos result of rate search
(0045) inverse: blk 1 ;flag that received data is inverted
(0046) batch_cnt: blk 1 ;counter of batches have been received
(0047)
(0048) area text(ROM,REL) ;inform assembler that program code follws
(0049)
(0050) ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
(0051) ; Name : _main
(0052) ; Desc. : Main function for POCSAG Decoder
(0053) ; Input : None
(0054) ; Output : None
(0055) ; Operation : Called from boot.asm after initialization. It will find POCSAG data
(0056) ; packet, synchronize to it, and copy into UART
(0057) ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
(0058) _main:
(0059) ;UART Init: 9600, 8-N-1
(0060) mov A,0
__text_start:
_main:
0100: 50 00 MOV A,0
(0061) call TX8_1_Start
0102: 91 D2 CALL _TX8_1_Start
(0062) call Counter8_2_Start
0104: 93 4C CALL _Counter8_2_Start
(0063)
(0064) ;Comparator Init:
(0065) mov A, CMPPRG_1_HIGHPOWER
0106: 50 03 MOV A,3
(0066) call CMPPRG_1_SetPower
0108: 93 94 CALL CMPPRG_1_Start
(0067) mov A, CMPPRG_1_REF0_312
010A: 50 40 MOV A,64
(0068) call CMPPRG_1_SetRef
010C: 93 9E CALL _CMPPRG_1_SetRef
(0069)
(0070) ;PGA Init
(0071) mov A, PGA_1_HIGHPOWER
010E: 50 03 MOV A,3
(0072) call PGA_1_Start
0110: 93 0D CALL _PGA_1_SetPower
(0073) mov A, PGA_1_G2_00
0112: 50 78 MOV A,120
(0074) call PGA_1_SetGain
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -