pocsag_decoder.lst

A very good POCSAG Paging Protocol Decoder.

    0000: 80 4E    JMP   0x004F
    0002: 30       HALT  
    0003: 30       HALT  
FILE: C:\PROGRA~1\CYPRES~1\PSOCDE~1\PROJECTS\POCSAG~1\BOOT.ASM
(0001) ;$Id: //depot/Rel_3.1/BuildMediaPSoC/Executables/Templates/boot.tpl#3 $
(0002) ;=============================================================================
(0003) ;  FILENAME:   boot.asm
(0004) ;   VERSION:   3.06
(0005) ;      DATE:   2 April 2002
(0006) ;
(0007) ;  DESCRIPTION:
(0008) ;   M8C Boot Code from Reset.
(0009) ;
(0010) ;   Copyright (c) Cypress MicroSystems 2001, 2002. All rights reserved.
(0011) ;
(0012) ; NOTES:
(0013) ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
(0014) ; the project's root directory to create BOOT.ASM. Any changes made to 
(0015) ; BOOT.ASM will be  overwritten every time the project is generated; therfore
(0016) ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
(0017) ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
(0018) ; are not accidentally modified.
(0019) ;
(0020) ; The start of _main is at a fixed location so care must be taken when adding
(0021) ; user code for the Sleep Interrupt. If too much code is added, the end of 
(0022) ; BOOT.ASM will extend into _main and cause a linker error. The safest way
(0023) ; to add code for the Sleep Interrupt is to CALL a separate routine that 
(0024) ; contains the desired additional Sleep Interrupt code.
(0025) ;=============================================================================
(0026) 
(0027) include ".\lib\pocsag_decoder_GlobalParams.inc"
(0028) include "m8c.inc"
(0029) include "m8ssc.inc"
(0030) 
(0031) ;-----------------------------------------------------------------------------
(0032) ; Optimization flags
(0033) ;-----------------------------------------------------------------------------
(0034) 
(0035) C_LANGUAGE_SUPPORT: equ 1         ;Set to 0 to optimize for ASM only
(0036) 
(0037) ;-----------------------------------------------------------------------------
(0038) ; Export Declarations
(0039) ;-----------------------------------------------------------------------------
(0040) 
(0041) export __start
(0042) export _exit
(0043) export __bss_start
(0044) 
(0045) export __lit_start
(0046) export __idata_start
(0047) export __data_start
(0048) export __func_lit_start
(0049) export __text_start
(0050) 
(0051) 
(0052) ;-----------------------------------------------------------------------------
(0053) ; Interrupt Vector Table
(0054) ;-----------------------------------------------------------------------------
(0055) ;
(0056) ; Interrupt vector table entries are 4 bytes long and contain the code
(0057) ; that services the interrupt (or causes it to be serviced).
(0058) ;
(0059) ;-----------------------------------------------------------------------------
(0060) 
(0061) 
(0062)     AREA    TOP(ROM, ABS)
(0063) 
(0064)     org 0                         ;Reset Interrupt Vector
(0065)     jmp __start                   ;First instruction executed following a Reset
(0066) 
(0067)     org 04h                       ;Supply Monitor Interrupt Vector
(0068)     halt                          ;Stop execution if power falls too low
    0004: 30       HALT  
(0069)     reti
    0005: 7E       RETI  
    0006: 30       HALT  
    0007: 30       HALT  
(0070) 
(0071)     org 08h                       ;PSoC Block DBA00 Interrupt Vector
(0072)     ljmp	TIMER8_1_ISR          ;Timer interrupt routine
    0008: 7D 02 6F LJMP  TIMER8_1_ISR
(0073)     reti
    000B: 7E       RETI  
(0074) 
(0075)     org 0Ch                       ;PSoC Block DBA01 Interrupt Vector
(0076)     // call	void_handler
(0077)     reti
    000C: 7E       RETI  
    000D: 30       HALT  
    000E: 30       HALT  
    000F: 30       HALT  
(0078) 
(0079)     org 10h                       ;PSoC Block DBA02 Interrupt Vector
(0080)     // call	void_handler
(0081)     reti
    0010: 7E       RETI  
    0011: 30       HALT  
    0012: 30       HALT  
    0013: 30       HALT  
(0082) 
(0083)     org 14h                       ;PSoC Block DBA03 Interrupt Vector
(0084)     ljmp	Counter8_2INT
    0014: 7D 04 3F LJMP  Counter8_2INT
(0085)     reti
    0017: 7E       RETI  
(0086) 
(0087)     org 18h                       ;PSoC Block DCA04 Interrupt Vector
(0088)     ljmp	TX8_1INT
    0018: 7D 02 C3 LJMP  TX8_1INT
(0089)     reti
    001B: 7E       RETI  
(0090) 
(0091)     org 1Ch                       ;PSoC Block DCA05 Interrupt Vector
(0092)     // call	void_handler
(0093)     reti
    001C: 7E       RETI  
    001D: 30       HALT  
    001E: 30       HALT  
    001F: 30       HALT  
(0094) 
(0095)     org 20h                       ;PSoC Block DCA06 Interrupt Vector
(0096)     // call	void_handler
(0097)     reti
    0020: 7E       RETI  
    0021: 30       HALT  
    0022: 30       HALT  
    0023: 30       HALT  
(0098) 
(0099)     org 24h                       ;PSoC Block DCA07 Interrupt Vector
(0100)     // call	void_handler
(0101)     reti
    0024: 7E       RETI  
    0025: 30       HALT  
    0026: 30       HALT  
    0027: 30       HALT  
(0102) 
(0103)     org 28h                       ;Analog Column 0 Interrupt Vector
(0104)     ljmp    COMP_ISR              ;comparator interrupt routine
    0028: 7D 02 AF LJMP  COMP_ISR
(0105)     reti
    002B: 7E       RETI  
(0106) 
(0107)     org 2Ch                       ;Analog Column 1 Interrupt Vector
(0108)     // call	void_handler
(0109)     reti
    002C: 7E       RETI  
    002D: 30       HALT  
    002E: 30       HALT  
    002F: 30       HALT  
(0110) 
(0111)     org 30h                       ;Analog Column 2 Interrupt Vector
(0112)     // call	void_handler
(0113)     reti
    0030: 7E       RETI  
    0031: 30       HALT  
    0032: 30       HALT  
    0033: 30       HALT  
(0114) 
(0115)     org 34h                       ;Analog Column 3 Interrupt Vector
(0116)     // call	void_handler
(0117)     reti
    0034: 7E       RETI  
    0035: 30       HALT  
    0036: 30       HALT  
    0037: 30       HALT  
(0118) 
(0119)     org 38h                       ;GPIO Interrupt Vector
(0120)     ljmp	GPIO_ISR              ;input port interrupt routine
    0038: 7D 02 7D LJMP  GPIO_ISR
(0121)     reti
    003B: 7E       RETI  
(0122) 
(0123)     org 3Ch                       ;Sleep Timer Interrupt Vector
(0124)     jmp SleepTimerISR
    003C: 80 02    JMP   0x003F
(0125)     reti
    003E: 7E       RETI  
(0126) 
(0127) ;-----------------------------------------------------------------------------
(0128) ;  Sleep Timer ISR
(0129) ;-----------------------------------------------------------------------------
(0130) ;  This code uses conditional compiler flags to enable code to initialize the 
(0131) ;  External Crystal Oscillator (ECO) and the PLL_Lock mode of the Internal 
(0132) ;  Main Oscillator (IMO).  If the ECO and the IMO PLL_Lock mode are not used,
(0133) ;  the initialization code is not compiled.
(0134) ;-----------------------------------------------------------------------------
(0135) IF SELECT_32K
(0136)     export  _ClockNotStable
(0137)     FIRST_TIME:       equ  2h
(0138)     SECOND_TIME:      equ  1h
(0139)     CLOCK_STABLE:     equ  0h
(0140) ENDIF
(0141) 
(0142) SleepTimerISR:
(0143)     push A
    003F: 08       PUSH  A
(0144) 
(0145)     NO_USER_SLEEP_ISR:  equ  0    ;Change this equate to 0 if adding ISR
(0146) 	//Sleep timer interrupt is used only ones during power-on test. //
(0147) 	// See NOTES at the top of this file.           //
(0148) 
(0149)     IF SELECT_32K
(0150)         mov A,[ClockNotStable]    ;ClockNotStable is also state of clock init
(0151)         jz   NormalSleep
(0152)         IF PLL_MODE        
(0153)             dec A
(0154)             jz  SecondTime        ;This case is only needed if PLL_Lock
(0155)         ENDIF
(0156)             jmp  FirstTime        ;This case is only needed if the ECO is used
(0157)     ENDIF
(0158) 
(0159) NormalSleep:
(0160)     pop A                         ;normal sleep 
    0040: 18       POP   A
    0041: 5D FF    MOV   A,REG[255]
    0043: 70 FE    AND   F,254
    0045: 41 E0 BF AND   REG[224],191
    0048: 21 80    AND   A,128
    004A: A0 03    JZ    0x004E
    004C: 71 01    OR    F,1
(0161)     M8C_DisableIntMask INT_MSK0,INT_MSK0_Sleep         ;disable sleep timer interrupt
(0162)     reti
    004E: 7E       RETI  
(0163) 
(0164)    IF SELECT_32K
(0165)    FirstTime:
(0166)    ; 1st time through the SleepISR. Will arrive here 1 second after boot
(0167)    ; the External Crystal Oscillator (ECO) is now stable.
(0168)    ; If both ECO and PLL_Lock, then turn on PLL_Lock and wait for it to 
(0169)    ; stabilize. Set SleepClock to 64 Hz, set PLL Mode bit, set CPU_Clock to
(0170)    ; 3 MHz, set ClockNotStable to SECOND_TIME. The clock initialization is
(0171)    ; not yet complete.
(0172)    ; If ECO but not PLL_Lock, set SleepClock to user selection, set 
(0173)    ; ClockNotStable to CLOCK_STABLE. The clock initialization is complete.
(0174) 
(0175)       IF PLL_MODE
(0176)          M8C_SetBank1
(0177)          IF (CPU_CLOCK_JUST & 04h)   ;CPU setting in Device Editor is <3MHz
(0178)             ;Enable PLL, set sleep timer to 64Hz and CPU per Device Editor
(0179)             mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_Sleep_64Hz |CPU_CLOCK_JUST)
(0180)          ELSE             ;CPU setting in Device Editor is >=3MHz
(0181)             ;Enable PLL, set sleep timer to 64Hz and CPU clock to 3MHz
(0182)             mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_Sleep_64Hz | OSC_CR0_CPU_3MHz)
(0183)          ENDIF
(0184)          M8C_SetBank0
(0185)          mov [ClockNotStable],SECOND_TIME
(0186)       ELSE
(0187)          ;Set the sleep timer, PLL (disabled) & CPU per Device Editor
(0188)          M8C_SetBank1
(0189)          mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
(0190)          M8C_SetBank0
(0191)          mov [ClockNotStable],CLOCK_STABLE
(0192)          IF NO_USER_SLEEP_ISR     ;turn off Sleep Int if no longer needed
(0193)             M8C_DisableIntMask INT_MSK0,INT_MSK0_Sleep
(0194)          ENDIF
(0195)       ENDIF
(0196)       pop A
(0197)       reti
(0198)    ENDIF
(0199)    
(0200)    IF PLL_MODE
(0201) SecondTime:    
(0202)       ; 2nd time through SleepISR. Compiled only if PLL_Mode set to Ext Lock
(0203)       M8C_SetBank1
(0204)       ; Set the sleep timer and CPU per Device Editor
(0205)       mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
(0206)       M8C_SetBank0
(0207)       mov [_ClockNotStable],CLOCK_STABLE
(0208)       IF NO_USER_SLEEP_ISR
(0209)          M8C_DisableIntMask INT_MSK0,INT_MSK0_Sleep
(0210)       ENDIF
(0211)       pop A
(0212)       reti
(0213)    ENDIF
(0214) 
(0215)    IF (PLL_MODE & ~SELECT_32K)
(0216)       These lines intentionally generate syntax errors to alert you that you
(0217)       have selected an invalid state.  Setting PLL Mode to Ext Lock without
(0218)       32K_Select set to External is not allowed.
(0219)    ENDIF
(0220) 
(0221) ;-----------------------------------------------------------------------------
(0222) ;  Start of Execution
(0223) ;-----------------------------------------------------------------------------
(0224) __start:
(0225)     mov A,__bss_end               ;Set top of stack to end of used RAM
    004F: 50 0E    MOV   A,14
(0226)     swap SP,A
    0051: 4E       SWAP  SP,A
    0052: 71 10    OR    F,16
(0227)     ;-------------------------------------------------------------------------
(0228)     ; Set clock trim if the operating voltage is 3.3V. On power up, 5V is
(0229)     ; loaded, so this is only needed for 3.3V operation.
(0230)     ;-------------------------------------------------------------------------
(0231)     IF (SUPPLY_VOLTAGE)               ; 1 means 5.0V
(0232)     ELSE                              ; 0 means 3.3V
(0233)        mov  [bSSC_TABLE_TableId], 1   ; Point to the Trim table
(0234)        SSC_Action TABLE_READ          ; Perform a table read supervisor call
(0235)        M8C_SetBank1
(0236)        mov  A, [OSCILLATOR_TRIM_3V]   
(0237)        mov  reg[IMO_TR], A            ; Load the 3V trim oscillator setting
(0238)        mov  A, [VOLTAGE_TRIM_3V]
(0239)        mov  reg[BDG_TR], A            ; Load the bandgap trim setting for 3V
(0240)        IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0241)        ELSE
(0242)           These lines intentionally generate syntax errors to alert you
(0243)           that you have selected an invalid state.  The CPU_CLock cannot
(0244)           be run at 24 MHz when the chip operating voltage is below 4.75V
(0245)        ENDIF
(0246)     ENDIF
(0247) 
(0248) 
(0249)     ;-------------------------------------------------------------------------
(0250)     ; Initialize oscillator register
(0251)     ;-------------------------------------------------------------------------
(0252)     IF SELECT_32K
(0253)        ;If 32K is set to External, turn the pins used by the crystal to Hi-Z.
(0254)        ;Then, set the sleep timer to 1Hz & reset the sleep timer.  (Don't turn
(0255)        ;on the ECO yet, because if the Sleep Timer happens to time out it will
(0256)        ;enable the ECO too soon).  Then enable ECO, enable sleep interrupt,