📄 main.lis
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0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register (RW)
0080 OSC_CR0_32K_Select: equ 80h ; MASK: Enable/Disable External XTAL Oscillator
0040 OSC_CR0_PLL_Mode: equ 40h ; MASK: Enable/Disable PLL
0018 OSC_CR0_Sleep: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_Sleep_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_Sleep_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_Sleep_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_Sleep_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System V1/V2 Divider Control Register (RW)
00F0 OSC_CR1_V1: equ F0h ; MASK System V1 24MHz divider
000F OSC_CR1_V2: equ 0Fh ; MASK System V2 24MHz divider
0000
0000 ;Reserved equ E2h
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (WO)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (WO)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (WO)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (WO)
0000
0000
0000
0000 ;;===================================
0000 ;; M8C System Macros
0000 ;;===================================
0000
0000
0000 ;-------------------------------
0000 ; Swapping Register Banks
0000 ;-------------------------------
0000
0000 macro M8C_SetBank0
0000 and F, ~FlagXIOMask
0000 macro M8C_SetBank1
0000 or F, FlagXIOMask
0000 macro M8C_EnableGInt
0000 or F, FlagGlobalIE
0000 macro M8C_DisableGInt
0000 and F, ~FlagGlobalIE
0001 DISABLE_INT_FIX: equ 1
0000 ;---------------------------------------------------
0000 ; Use the following macros to enable/disable
0000 ; either of the two global interrupt mask registers,
0000 ; INT_MSK0 or INT_MSK1.
0000 ;
0000 ; This is a fix to a noted problem in which an
0000 ; inadvertant reset can occur if an interrupt occurs
0000 ; while clearing an interrupt mask bit.
0000 ;
0000 ; Usage: M8C_DisableIntMask INT_MSKN, MASK
0000 ; M8C_EnableIntMask INT_MSKN, MASK
0000 ;
0000 ; where INT_MSKN is INT_MSK0 or INT_MSK1 and
0000 ; MASK is the bit set to enable or disable
0000 ;-------------------------------------------------
0000 ; Disable Interrupt Bit Mask(s)
0000 macro M8C_DisableIntMask
0000 if DISABLE_INT_FIX
0000 mov A, reg[CPU_SCR] ; save the current Global interrupt state
0000 M8C_DisableGInt ; disable global interrupts
0000 endif
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 if DISABLE_INT_FIX
0000 and A, CPUSCR_GIEMask ; determine if global interrupt was set
0000 jz . + 4 ; jump if global interrupt disabled
0000 M8C_EnableGInt ; set global interrupt
0000 endif
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1
0000 macro M8C_EnableWatchDog
0000 ; Clearing the Power-On Reset bit starts up the Watchdog timer
0000 ; See the 25xxx/26xxx Family Datasheet, Section 9.3.4.
0000 and reg[CPU_SCR], ~CPUSCR_PORSMask & ~CPUSCR_WDRSMask
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR], CPUSCR_SleepMask
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then RIP.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR], CPUSCR_StopMask
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore everything to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro SSC
0000 db 0
0000 CMPPRG_1_OFF: equ 0
0001 CMPPRG_1_LOWPOWER: equ 1
0002 CMPPRG_1_MEDPOWER: equ 2
0003 CMPPRG_1_HIGHPOWER: equ 3
0000
00F0 CMPPRG_1_REF1_000: equ f0h
00E0 CMPPRG_1_REF0_937: equ e0h
00D0 CMPPRG_1_REF0_875: equ d0h
00C0 CMPPRG_1_REF0_812: equ c0h
00B0 CMPPRG_1_REF0_750: equ b0h
00A0 CMPPRG_1_REF0_688: equ a0h
0090 CMPPRG_1_REF0_625: equ 90h
0080 CMPPRG_1_REF0_562: equ 80h
0070 CMPPRG_1_REF0_500: equ 70h
0060 CMPPRG_1_REF0_437: equ 60h
0050 CMPPRG_1_REF0_375: equ 50h
0040 CMPPRG_1_REF0_312: equ 40h
0030 CMPPRG_1_REF0_250: equ 30h
0020 CMPPRG_1_REF0_188: equ 20h
0010 CMPPRG_1_REF0_125: equ 10h
0000 CMPPRG_1_REF0_062: equ 00h
0000
0071 CMPPRG_1_COMP_CR0: equ 71h
0072 CMPPRG_1_COMP_CR1: equ 72h
0073 CMPPRG_1_COMP_CR2: equ 73h
0000
0001 bTimer8_1_INT_MASK: equ 01h
0000 ;timer8 interrupt address
00E1 Timer8_1_INT_REG: equ 0e1h
0000
0000 ;---------------------------------
0000 ; Registers used by timer8
0000 ;---------------------------------
0023 Timer8_1_CONTROL_REG: equ 23h ;Control register
0020 Timer8_1_COUNTER_REG: equ 20h ;Counter register
0021 Timer8_1_PERIOD_REG: equ 21h ;Period value register
0022 Timer8_1_COMPARE_REG: equ 22h ;CompareValue register
0020 Timer8_1_FUNC_REG: equ 20h ;Function register
0021 Timer8_1_INPUT_REG: equ 21h ;Input register
0022 Timer8_1_OUTPUT_REG: equ 22h ;Output register
0000
0000 ; end of file
0000
0010 bTX8_1_INT_MASK: equ 10h
0000 ;TX8 interrupt address
00E1 TX8_1_INT_REG: equ 0e1h
0000
0000 ;------------------------------------
0000 ; Transmitter Parity masks
0000 ;------------------------------------
0000 TX8_PARITY_NONE: equ 00h
0002 TX8_PARITY_EVEN: equ 02h
0006 TX8_PARITY_ODD: equ 06h
0000
0000 ;------------------------------------
0000 ; Transmitter Status Register masks
0000 ;------------------------------------
0020 TX8_TX_COMPLETE: equ 20h
0010 TX8_TX_BUFFER_EMPTY: equ 10h
0000
0000 ;---------------------------------
0000 ; Registers used by TX8
0000 ;---------------------------------
0033 TX8_1_CONTROL_REG: equ 33h ;Control register
0030 TX8_1_TX_SHIFT_REG: equ 30h ;TX Shift Register register
0031 TX8_1_TX_BUFFER_REG: equ 31h ;TX Buffer Register
0030 TX8_1_FUNC_REG: equ 30h ;Function register
0031 TX8_1_INPUT_REG: equ 31h ;Input register
0032 TX8_1_OUTPUT_REG: equ 32h ;Output register
0000
0000 ; end of file
0000 PGA_1_OFF: equ 0
0001 PGA_1_LOWPOWER: equ 1
0002 PGA_1_MEDPOWER: equ 2
0003 PGA_1_HIGHPOWER: equ 3
0000
0008 PGA_1_G16_0: equ 08h
0018 PGA_1_G8_00: equ 18h
0028 PGA_1_G5_33: equ 28h
0038 PGA_1_G4_00: equ 38h
0048 PGA_1_G3_20: equ 48h
0058 PGA_1_G2_67: equ 58h
0068 PGA_1_G2_27: equ 68h
0078 PGA_1_G2_00: equ 78h
0088 PGA_1_G1_78: equ 88h
0098 PGA_1_G1_60: equ 98h
00A8 PGA_1_G1_46: equ A8h
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