ar5210var.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

/*	$OpenBSD: ar5210var.h,v 1.11 2005/12/18 17:59:58 reyk Exp $	*/

/*
 * Copyright (c) 2004, 2005 Reyk Floeter <[e-mail]>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Specific definitions for the Atheros AR5000 Wireless LAN chipset
 * (AR5210 + AR5110).
 */

#ifndef _AR5K_AR5210_VAR_H
#define _AR5K_AR5210_VAR_H

#include "ar5xxx.h"

/*
 * Define a "magic" code for the AR5210 (the HAL layer wants it)
 */

#define AR5K_AR5210_MAGIC		0x0000145a /* 5210 */
#define AR5K_AR5210_TX_NUM_QUEUES	2

#if BYTE_ORDER == BIG_ENDIAN
#define AR5K_AR5210_INIT_CFG	(					\
	AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWRD			\
)
#else
#define AR5K_AR5210_INIT_CFG	0x00000000
#endif

/*
 * Internal RX/TX descriptor structures
 * (rX: reserved fields possibily used by future versions of the ar5k chipset)
 */

struct ar5k_ar5210_rx_desc {
	/*
	 * RX control word 0
	 */
	u_int32_t	rx_control_0;

#define AR5K_AR5210_DESC_RX_CTL0			0x00000000

	/*
	 * RX control word 1
	 */
	u_int32_t	rx_control_1;

#define AR5K_AR5210_DESC_RX_CTL1_BUF_LEN		0x00000fff
#define AR5K_AR5210_DESC_RX_CTL1_INTREQ			0x00002000
} __packed;

struct ar5k_ar5210_rx_status {
	/*
	 * RX status word 0
	 */
	u_int32_t	rx_status_0;

#define AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN		0x00000fff
#define AR5K_AR5210_DESC_RX_STATUS0_MORE		0x00001000
#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA	0x00004000
#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE	0x00078000
#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE_S	15
#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL	0x07f80000
#define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL_S	19

	/*
	 * RX status word 1
	 */
	u_int32_t	rx_status_1;

#define AR5K_AR5210_DESC_RX_STATUS1_DONE		0x00000001
#define AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK	0x00000002
#define AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR		0x00000004
#define AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN	0x00000008
#define AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR	0x00000010
#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR		0x000000e0
#define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR_S		5
#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID	0x00000100
#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX		0x00007e00
#define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_S		9
#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP	0x0fff8000
#define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S	15
#define AR5K_AR5210_DESC_RX_STATUS1_KEY_CACHE_MISS	0x10000000
} __packed;

#define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE		0x00
#define AR5K_AR5210_DESC_RX_PHY_ERROR_TIMING		0x20
#define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY		0x40
#define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE		0x60
#define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH		0x80
#define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM		0xa0
#define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE		0xc0
#define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR	0xe0

struct ar5k_ar5210_tx_desc {
	/*
	 * TX control word 0
	 */
	u_int32_t	tx_control_0;

#define AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN		0x00000fff
#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN		0x0003f000
#define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN_S		12
#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE		0x003c0000
#define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE_S		18
#define AR5K_AR5210_DESC_TX_CTL0_RTSENA			0x00400000
#define AR5K_AR5210_DESC_TX_CTL0_LONG_PACKET		0x00800000
#define AR5K_AR5210_DESC_TX_CTL0_CLRDMASK		0x01000000
#define AR5K_AR5210_DESC_TX_CTL0_ANT_MODE_XMIT		0x02000000
#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE		0x1c000000
#define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE_S		26
#define AR5K_AR5210_DESC_TX_CTL0_INTREQ			0x20000000
#define AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID	0x40000000

	/*
	 * TX control word 1
	 */
	u_int32_t	tx_control_1;

#define AR5K_AR5210_DESC_TX_CTL1_BUF_LEN		0x00000fff
#define AR5K_AR5210_DESC_TX_CTL1_MORE			0x00001000
#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX	0x0007e000
#define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S	13
#define AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION		0xfff80000
} __packed;

#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL   0x00
#define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM     0x04
#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL   0x08
#define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c
#define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS     0x10

struct ar5k_ar5210_tx_status {
	/*
	 * TX status word 0
	 */
	u_int32_t	tx_status_0;

#define AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001
#define AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002
#define AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004
#define AR5K_AR5210_DESC_TX_STATUS0_FILTERED		0x00000008
#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT	0x000000f0
#define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S	4
#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT	0x00000f00
#define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT_S	8
#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000
#define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16

	/*
	 * TX status word 1
	 */
	u_int32_t	tx_status_1;

#define AR5K_AR5210_DESC_TX_STATUS1_DONE		0x00000001
#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe
#define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM_S		1
#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000
#define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
} __packed;

/*
 * Public function prototypes
 */
extern ar5k_attach_t ar5k_ar5210_attach;

/*
 * Initial mode settings ("Base Mode" or "Turbo Mode")
 */

#define AR5K_AR5210_INI_MODE(_aifs) {					\
	{ AR5K_AR5210_SLOT_TIME,					\
	    AR5K_INIT_SLOT_TIME,					\
	    AR5K_INIT_SLOT_TIME_TURBO },				\
	{ AR5K_AR5210_SLOT_TIME,					\
	    AR5K_INIT_ACK_CTS_TIMEOUT,					\
	    AR5K_INIT_ACK_CTS_TIMEOUT_TURBO },				\
	{ AR5K_AR5210_USEC,						\
	    AR5K_INIT_TRANSMIT_LATENCY,					\
	    AR5K_INIT_TRANSMIT_LATENCY_TURBO},				\
	{ AR5K_AR5210_IFS0,						\
	    ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME)		\
	    << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS,		\
	    ((AR5K_INIT_SIFS_TURBO + (_aifs) * AR5K_INIT_SLOT_TIME_TURBO) \
	    << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO },	\
	{ AR5K_AR5210_IFS1,						\
	    AR5K_INIT_PROTO_TIME_CNTRL,					\
	    AR5K_INIT_PROTO_TIME_CNTRL_TURBO },				\
	{ AR5K_AR5210_PHY(17),						\
	    (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C,	\
	    (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x38 },	\
	{ AR5K_AR5210_PHY_FC,						\
	    AR5K_AR5210_PHY_FC_SERVICE_ERR |				\
	    AR5K_AR5210_PHY_FC_TXURN_ERR |				\
	    AR5K_AR5210_PHY_FC_ILLLEN_ERR |				\
	    AR5K_AR5210_PHY_FC_ILLRATE_ERR |				\
	    AR5K_AR5210_PHY_FC_PARITY_ERR |				\
	    AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020,			\
	    AR5K_AR5210_PHY_FC_SERVICE_ERR |				\
	    AR5K_AR5210_PHY_FC_TXURN_ERR |				\
	    AR5K_AR5210_PHY_FC_ILLLEN_ERR |				\
	    AR5K_AR5210_PHY_FC_ILLRATE_ERR |				\
	    AR5K_AR5210_PHY_FC_PARITY_ERR |				\
	    AR5K_AR5210_PHY_FC_TURBO_MODE |				\
	    AR5K_AR5210_PHY_FC_TURBO_SHORT |				\
	    AR5K_AR5210_PHY_FC_TIMING_ERR | 0x2020 },			\