📄 ar5210reg.h
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/* * First BSSID register (MAC address, lower 32bits) */#define AR5K_AR5210_BSS_ID0 0x8008/* * Second BSSID register (MAC address in upper 16 bits) * * AID: Association ID */#define AR5K_AR5210_BSS_ID1 0x800c#define AR5K_AR5210_BSS_ID1_AID 0xffff0000#define AR5K_AR5210_BSS_ID1_AID_S 16/* * Backoff slot time register */#define AR5K_AR5210_SLOT_TIME 0x8010/* * ACK/CTS timeout register */#define AR5K_AR5210_TIME_OUT 0x8014#define AR5K_AR5210_TIME_OUT_ACK 0x00001fff#define AR5K_AR5210_TIME_OUT_ACK_S 0#define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000#define AR5K_AR5210_TIME_OUT_CTS_S 16/* * RSSI threshold register */#define AR5K_AR5210_RSSI_THR 0x8018#define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700#define AR5K_AR5210_RSSI_THR_BM_THR_S 8/* * Retry limit register */#define AR5K_AR5210_RETRY_LMT 0x801c#define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f#define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0#define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0#define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4#define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00#define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8#define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000#define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14#define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000#define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20/* * Transmit latency register */#define AR5K_AR5210_USEC 0x8020#define AR5K_AR5210_USEC_1 0x0000007f#define AR5K_AR5210_USEC_1_S 0#define AR5K_AR5210_USEC_32 0x00003f80#define AR5K_AR5210_USEC_32_S 7#define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000#define AR5K_AR5210_USEC_TX_LATENCY_S 14#define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000#define AR5K_AR5210_USEC_RX_LATENCY_S 20/* * PCU beacon control register */#define AR5K_AR5210_BEACON 0x8024#define AR5K_AR5210_BEACON_PERIOD 0x0000ffff#define AR5K_AR5210_BEACON_PERIOD_S 0#define AR5K_AR5210_BEACON_TIM 0x007f0000#define AR5K_AR5210_BEACON_TIM_S 16#define AR5K_AR5210_BEACON_EN 0x00800000#define AR5K_AR5210_BEACON_RESET_TSF 0x01000000/* * CFP period register */#define AR5K_AR5210_CFP_PERIOD 0x8028/* * Next beacon time register */#define AR5K_AR5210_TIMER0 0x802c/* * Next DMA beacon alert register */#define AR5K_AR5210_TIMER1 0x8030/* * Next software beacon alert register */#define AR5K_AR5210_TIMER2 0x8034/* * Next ATIM window time register */#define AR5K_AR5210_TIMER3 0x8038/* * First inter frame spacing register (IFS) */#define AR5K_AR5210_IFS0 0x8040#define AR5K_AR5210_IFS0_SIFS 0x000007ff#define AR5K_AR5210_IFS0_SIFS_S 0#define AR5K_AR5210_IFS0_DIFS 0x007ff800#define AR5K_AR5210_IFS0_DIFS_S 11/* * Second inter frame spacing register (IFS) */#define AR5K_AR5210_IFS1 0x8044#define AR5K_AR5210_IFS1_PIFS 0x00000fff#define AR5K_AR5210_IFS1_PIFS_S 0#define AR5K_AR5210_IFS1_EIFS 0x03fff000#define AR5K_AR5210_IFS1_EIFS_S 12#define AR5K_AR5210_IFS1_CS_EN 0x04000000/* * CFP duration register */#define AR5K_AR5210_CFP_DUR 0x8048/* * Receive filter register */#define AR5K_AR5210_RX_FILTER 0x804c#define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001#define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002#define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004#define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008#define AR5K_AR5210_RX_FILTER_BEACON 0x00000010#define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020/* * Multicast filter register (lower 32 bits) */#define AR5K_AR5210_MCAST_FIL0 0x8050/* * Multicast filter register (higher 16 bits) */#define AR5K_AR5210_MCAST_FIL1 0x8054/* * Transmit mask register (lower 32 bits) */#define AR5K_AR5210_TX_MASK0 0x8058/* * Transmit mask register (higher 16 bits) */#define AR5K_AR5210_TX_MASK1 0x805c/* * Clear transmit mask */#define AR5K_AR5210_CLR_TMASK 0x8060/* * Trigger level register (before transmission) */#define AR5K_AR5210_TRIG_LVL 0x8064/* * PCU control register */#define AR5K_AR5210_DIAG_SW 0x8068#define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001#define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002#define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004#define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008#define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010#define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020#define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040#define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080#define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100#define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200#define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400#define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800#define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000#define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000/* * TSF (clock) register (lower 32 bits) */#define AR5K_AR5210_TSF_L32 0x806c/* * TSF (clock) register (higher 32 bits) */#define AR5K_AR5210_TSF_U32 0x8070/* * Last beacon timestamp register */#define AR5K_AR5210_LAST_TSTP 0x8080/* * Retry count register */#define AR5K_AR5210_RETRY_CNT 0x8084#define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f#define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0/* * Back-off status register */#define AR5K_AR5210_BACKOFF 0x8088#define AR5K_AR5210_BACKOFF_CW 0x000003ff#define AR5K_AR5210_BACKOFF_CNT 0x03ff0000/* * NAV register (current) */#define AR5K_AR5210_NAV 0x808c/* * RTS success register */#define AR5K_AR5210_RTS_OK 0x8090/* * RTS failure register */#define AR5K_AR5210_RTS_FAIL 0x8094/* * ACK failure register */#define AR5K_AR5210_ACK_FAIL 0x8098/* * FCS failure register */#define AR5K_AR5210_FCS_FAIL 0x809c/* * Beacon count register */#define AR5K_AR5210_BEACON_CNT 0x80a0/* * Key table (WEP) register */#define AR5K_AR5210_KEYTABLE_0 0x9000#define AR5K_AR5210_KEYTABLE(n) (AR5K_AR5210_KEYTABLE_0 + ((n) << 5))#define AR5K_AR5210_KEYTABLE_OFF(_n, x) (AR5K_AR5210_KEYTABLE(_n) + (x << 2))#define AR5K_AR5210_KEYTABLE_TYPE(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 5)#define AR5K_AR5210_KEYTABLE_TYPE_40 0x00000000#define AR5K_AR5210_KEYTABLE_TYPE_104 0x00000001#define AR5K_AR5210_KEYTABLE_TYPE_128 0x00000003#define AR5K_AR5210_KEYTABLE_MAC0(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 6)#define AR5K_AR5210_KEYTABLE_MAC1(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 7)#define AR5K_AR5210_KEYTABLE_VALID 0x00008000#define AR5K_AR5210_KEYTABLE_SIZE 64#define AR5K_AR5210_KEYCACHE_SIZE 8/* * PHY register */#define AR5K_AR5210_PHY(_n) (0x9800 + ((_n) << 2))/* * PHY frame control register */#define AR5K_AR5210_PHY_FC 0x9804#define AR5K_AR5210_PHY_FC_TURBO_MODE 0x00000001#define AR5K_AR5210_PHY_FC_TURBO_SHORT 0x00000002#define AR5K_AR5210_PHY_FC_TIMING_ERR 0x01000000#define AR5K_AR5210_PHY_FC_PARITY_ERR 0x02000000#define AR5K_AR5210_PHY_FC_ILLRATE_ERR 0x04000000#define AR5K_AR5210_PHY_FC_ILLLEN_ERR 0x08000000#define AR5K_AR5210_PHY_FC_SERVICE_ERR 0x20000000#define AR5K_AR5210_PHY_FC_TXURN_ERR 0x40000000/* * PHY agility command register */#define AR5K_AR5210_PHY_AGC 0x9808#define AR5K_AR5210_PHY_AGC_DISABLE 0x08000000/* * PHY chip revision register */#define AR5K_AR5210_PHY_CHIP_ID 0x9818/* * PHY activation register */#define AR5K_AR5210_PHY_ACTIVE 0x981c#define AR5K_AR5210_PHY_ENABLE 0x00000001#define AR5K_AR5210_PHY_DISABLE 0x00000002/* * PHY signal register */#define AR5K_AR5210_PHY_SIG 0x9858#define AR5K_AR5210_PHY_SIG_FIRSTEP 0x0003f000#define AR5K_AR5210_PHY_SIG_FIRSTEP_S 12#define AR5K_AR5210_PHY_SIG_FIRPWR 0x03fc0000#define AR5K_AR5210_PHY_SIG_FIRPWR_S 18/* * PHY coarse agility control register */#define AR5K_AR5210_PHY_AGCCOARSE 0x985c#define AR5K_AR5210_PHY_AGCCOARSE_LO 0x00007f80#define AR5K_AR5210_PHY_AGCCOARSE_LO_S 7#define AR5K_AR5210_PHY_AGCCOARSE_HI 0x003f8000#define AR5K_AR5210_PHY_AGCCOARSE_HI_S 15/* * PHY agility control register */#define AR5K_AR5210_PHY_AGCCTL 0x9860#define AR5K_AR5210_PHY_AGCCTL_CAL 0x00000001#define AR5K_AR5210_PHY_AGCCTL_NF 0x00000002/* * PHY noise floor status register */#define AR5K_AR5210_PHY_NF 0x9864#define AR5K_AR5210_PHY_NF_M 0x000001ff#define AR5K_AR5210_PHY_NF_ACTIVE 0x00000100#define AR5K_AR5210_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5210_PHY_NF_M)#define AR5K_AR5210_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5210_PHY_NF_M) + 1)/* * PHY ADC saturation register */#define AR5K_AR5210_PHY_ADCSAT 0x9868#define AR5K_AR5210_PHY_ADCSAT_ICNT 0x0001f800#define AR5K_AR5210_PHY_ADCSAT_ICNT_S 11#define AR5K_AR5210_PHY_ADCSAT_THR 0x000007e0#define AR5K_AR5210_PHY_ADCSAT_THR_S 5/* * PHY RF stage register */#define AR5K_AR5210_PHY_RFSTG 0x98d4#define AR5K_AR5210_PHY_RFSTG_DISABLE 0x00000021/* * Misc PHY/radio registers */#define AR5K_AR5210_BB_GAIN(_n) (0x9b00 + ((_n) << 2))#define AR5K_AR5210_RF_GAIN(_n) (0x9a00 + ((_n) << 2))#endif⌨️ 快捷键说明
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