ar5211reg.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

/*	$OpenBSD: ar5211reg.h,v 1.8 2005/12/18 17:59:58 reyk Exp $	*/

/*
 * Copyright (c) 2004, 2005 Reyk Floeter <[e-mail]>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Known registers of the Atheros AR5001 Wireless LAN chipsets
 * (AR5211/AR5311).
 */

#ifndef _AR5K_AR5211_REG_H
#define _AR5K_AR5211_REG_H

/*
 * Command register
 */
#define AR5K_AR5211_CR		0x0008
#define AR5K_AR5211_CR_RXE	0x00000004
#define AR5K_AR5211_CR_RXD	0x00000020
#define AR5K_AR5211_CR_SWI	0x00000040

/*
 * Receive queue descriptor pointer register
 */
#define AR5K_AR5211_RXDP	0x000c

/*
 * Configuration and status register
 */
#define AR5K_AR5211_CFG			0x0014
#define AR5K_AR5211_CFG_SWTD		0x00000001
#define AR5K_AR5211_CFG_SWTB		0x00000002
#define AR5K_AR5211_CFG_SWRD		0x00000004
#define AR5K_AR5211_CFG_SWRB		0x00000008
#define AR5K_AR5211_CFG_SWRG		0x00000010
#define AR5K_AR5211_CFG_ADHOC		0x00000020
#define AR5K_AR5211_CFG_PHY_OK		0x00000100
#define AR5K_AR5211_CFG_EEBS		0x00000200
#define	AR5K_AR5211_CFG_CLKGD		0x00000400
#define	AR5K_AR5211_CFG_PCI_THRES	0x00060000
#define	AR5K_AR5211_CFG_PCI_THRES_S	17

/*
 * Interrupt enable register
 */
#define AR5K_AR5211_IER		0x0024
#define AR5K_AR5211_IER_DISABLE	0x00000000
#define AR5K_AR5211_IER_ENABLE	0x00000001

/*
 * First RTS duration register
 */
#define AR5K_AR5211_RTSD0	0x0028
#define	AR5K_AR5211_RTSD0_6	0x000000ff
#define	AR5K_AR5211_RTSD0_6_S	0
#define	AR5K_AR5211_RTSD0_9	0x0000ff00
#define	AR5K_AR5211_RTSD0_9_S	8
#define	AR5K_AR5211_RTSD0_12	0x00ff0000
#define	AR5K_AR5211_RTSD0_12_S	16
#define	AR5K_AR5211_RTSD0_18	0xff000000
#define	AR5K_AR5211_RTSD0_18_S	24

/*
 * Second RTS duration register
 */
#define AR5K_AR5211_RTSD1	0x002c
#define	AR5K_AR5211_RTSD1_24	0x000000ff
#define	AR5K_AR5211_RTSD1_24_S	0
#define	AR5K_AR5211_RTSD1_36	0x0000ff00
#define	AR5K_AR5211_RTSD1_36_S	8
#define	AR5K_AR5211_RTSD1_48	0x00ff0000
#define	AR5K_AR5211_RTSD1_48_S	16
#define	AR5K_AR5211_RTSD1_54	0xff000000
#define	AR5K_AR5211_RTSD1_54_S	24

/*
 * Transmit configuration register
 */
#define AR5K_AR5211_TXCFG		0x0030
#define AR5K_AR5211_TXCFG_SDMAMR	0x00000007
#define AR5K_AR5211_TXCFG_SDMAMR_S	0
#define AR5K_AR5211_TXCFG_B_MODE	0x00000008
#define AR5K_AR5211_TXCFG_TXFULL	0x000003f0
#define AR5K_AR5211_TXCFG_TXFULL_S	4
#define AR5K_AR5211_TXCFG_TXFULL_0B	0x00000000
#define AR5K_AR5211_TXCFG_TXFULL_64B	0x00000010
#define AR5K_AR5211_TXCFG_TXFULL_128B	0x00000020
#define AR5K_AR5211_TXCFG_TXFULL_192B	0x00000030
#define AR5K_AR5211_TXCFG_TXFULL_256B	0x00000040
#define AR5K_AR5211_TXCFG_TXCONT_ENABLE	0x00000080
#define AR5K_AR5211_TXCFG_DMASIZE	0x00000100
#define AR5K_AR5211_TXCFG_JUMBO_TXE	0x00000400
#define AR5K_AR5211_TXCFG_RTSRND	0x00001000
#define AR5K_AR5211_TXCFG_FRMPAD_DIS	0x00002000
#define AR5K_AR5211_TXCFG_RDY_DIS	0x00004000

/*
 * Receive configuration register
 */
#define AR5K_AR5211_RXCFG			0x0034
#define AR5K_AR5211_RXCFG_SDMAMW		0x00000007
#define AR5K_AR5211_RXCFG_SDMAMW_S		0
#define	AR5K_AR5311_RXCFG_DEFAULT_ANTENNA	0x00000008
#define AR5K_AR5211_RXCFG_ZLFDMA		0x00000010
#define AR5K_AR5211_RXCFG_JUMBO_RXE		0x00000020
#define AR5K_AR5211_RXCFG_JUMBO_WRAP		0x00000040

/*
 * Receive jumbo descriptor last address register
 */
#define AR5K_AR5211_RXJLA		0x0038

/*
 * MIB control register
 */
#define AR5K_AR5211_MIBC		0x0040
#define AR5K_AR5211_MIBC_COW		0x00000001
#define AR5K_AR5211_MIBC_FMC		0x00000002
#define AR5K_AR5211_MIBC_CMC		0x00000004
#define AR5K_AR5211_MIBC_MCS		0x00000008

/*
 * Timeout prescale register
 */
#define AR5K_AR5211_TOPS		0x0044
#define	AR5K_AR5211_TOPS_M		0x0000ffff

/*
 * Receive timeout register (no frame received)
 */
#define AR5K_AR5211_RXNOFRM		0x0048
#define	AR5K_AR5211_RXNOFRM_M		0x000003ff

/*
 * Transmit timeout register (no frame sent)
 */
#define AR5K_AR5211_TXNOFRM		0x004c
#define	AR5K_AR5211_TXNOFRM_M		0x000003ff
#define	AR5K_AR5211_TXNOFRM_QCU		0x000ffc00

/*
 * Receive frame gap timeout register
 */
#define AR5K_AR5211_RPGTO		0x0050
#define AR5K_AR5211_RPGTO_M		0x000003ff

/*
 * Receive frame count limit register
 */
#define AR5K_AR5211_RFCNT		0x0054
#define AR5K_AR5211_RFCNT_M		0x0000001f

/*
 * Misc settings register
 */
#define AR5K_AR5211_MISC		0x0058
#define	AR5K_AR5211_MISC_DMA_OBS_M	0x000001e0
#define	AR5K_AR5211_MISC_DMA_OBS_S	5
#define	AR5K_AR5211_MISC_MISC_OBS_M	0x00000e00
#define	AR5K_AR5211_MISC_MISC_OBS_S	9
#define	AR5K_AR5211_MISC_MAC_OBS_LSB_M	0x00007000
#define	AR5K_AR5211_MISC_MAC_OBS_LSB_S	12
#define	AR5K_AR5211_MISC_MAC_OBS_MSB_M	0x00038000
#define	AR5K_AR5211_MISC_MAC_OBS_MSB_S	15

/*
 * QCU/DCU clock gating register
 */
#define	AR5K_AR5311_QCUDCU_CLKGT
#define	AR5K_AR5311_QCUDCU_CLKGT_QCU	0x0000ffff
#define	AR5K_AR5311_QCUDCU_CLKGT_DCU	0x07ff0000

/*
 * Primary interrupt status register
 */
#define AR5K_AR5211_PISR		0x0080
#define AR5K_AR5211_PISR_RXOK		0x00000001
#define AR5K_AR5211_PISR_RXDESC		0x00000002
#define AR5K_AR5211_PISR_RXERR		0x00000004
#define AR5K_AR5211_PISR_RXNOFRM	0x00000008
#define AR5K_AR5211_PISR_RXEOL		0x00000010
#define AR5K_AR5211_PISR_RXORN		0x00000020
#define AR5K_AR5211_PISR_TXOK		0x00000040
#define AR5K_AR5211_PISR_TXDESC		0x00000080
#define AR5K_AR5211_PISR_TXERR		0x00000100
#define AR5K_AR5211_PISR_TXNOFRM	0x00000200
#define AR5K_AR5211_PISR_TXEOL		0x00000400
#define AR5K_AR5211_PISR_TXURN		0x00000800
#define AR5K_AR5211_PISR_MIB		0x00001000
#define AR5K_AR5211_PISR_SWI		0x00002000
#define AR5K_AR5211_PISR_RXPHY		0x00004000
#define AR5K_AR5211_PISR_RXKCM		0x00008000
#define AR5K_AR5211_PISR_SWBA		0x00010000
#define AR5K_AR5211_PISR_BRSSI		0x00020000
#define AR5K_AR5211_PISR_BMISS		0x00040000
#define AR5K_AR5211_PISR_HIUERR		0x00080000
#define AR5K_AR5211_PISR_BNR		0x00100000
#define AR5K_AR5211_PISR_TIM		0x00800000
#define AR5K_AR5211_PISR_GPIO		0x01000000
#define AR5K_AR5211_PISR_QCBRORN	0x02000000
#define AR5K_AR5211_PISR_QCBRURN	0x04000000
#define AR5K_AR5211_PISR_QTRIG		0x08000000

/*
 * Secondary interrupt status registers (0 - 4)
 */
#define AR5K_AR5211_SISR0		0x0084
#define AR5K_AR5211_SISR0_QCU_TXOK	0x000003ff
#define AR5K_AR5211_SISR0_QCU_TXDESC	0x03ff0000

#define AR5K_AR5211_SISR1		0x0088
#define AR5K_AR5211_SISR1_QCU_TXERR	0x000003ff
#define AR5K_AR5211_SISR1_QCU_TXEOL	0x03ff0000

#define AR5K_AR5211_SISR2		0x008c
#define AR5K_AR5211_SISR2_QCU_TXURN	0x000003ff
#define	AR5K_AR5211_SISR2_MCABT		0x00100000
#define	AR5K_AR5211_SISR2_SSERR		0x00200000
#define	AR5K_AR5211_SISR2_DPERR		0x00400000

#define AR5K_AR5211_SISR3		0x0090
#define AR5K_AR5211_SISR3_QCBRORN	0x000003ff
#define AR5K_AR5211_SISR3_QCBRURN	0x03ff0000

#define AR5K_AR5211_SISR4		0x0094
#define AR5K_AR5211_SISR4_QTRIG		0x000003ff

/*
 * Shadow read-and-clear interrupt status registers
 */
#define AR5K_AR5211_RAC_PISR	0x00c0
#define AR5K_AR5211_RAC_SISR0	0x00c4
#define AR5K_AR5211_RAC_SISR1	0x00c8
#define AR5K_AR5211_RAC_SISR2	0x00cc
#define AR5K_AR5211_RAC_SISR3	0c00d0
#define AR5K_AR5211_RAC_SISR4	0c00d4

/*
 * Primary interrupt mask register
 */
#define AR5K_AR5211_PIMR		0x00a0
#define AR5K_AR5211_PIMR_RXOK		0x00000001
#define AR5K_AR5211_PIMR_RXDESC		0x00000002
#define AR5K_AR5211_PIMR_RXERR		0x00000004
#define AR5K_AR5211_PIMR_RXNOFRM	0x00000008
#define AR5K_AR5211_PIMR_RXEOL		0x00000010
#define AR5K_AR5211_PIMR_RXORN		0x00000020
#define AR5K_AR5211_PIMR_TXOK		0x00000040
#define AR5K_AR5211_PIMR_TXDESC		0x00000080
#define AR5K_AR5211_PIMR_TXERR		0x00000100
#define AR5K_AR5211_PIMR_TXNOFRM	0x00000200
#define AR5K_AR5211_PIMR_TXEOL		0x00000400
#define AR5K_AR5211_PIMR_TXURN		0x00000800
#define AR5K_AR5211_PIMR_MIB		0x00001000
#define AR5K_AR5211_PIMR_SWI		0x00002000
#define AR5K_AR5211_PIMR_RXPHY		0x00004000
#define AR5K_AR5211_PIMR_RXKCM		0x00008000
#define AR5K_AR5211_PIMR_SWBA		0x00010000
#define AR5K_AR5211_PIMR_BRSSI		0x00020000
#define AR5K_AR5211_PIMR_BMISS		0x00040000
#define AR5K_AR5211_PIMR_HIUERR		0x00080000
#define AR5K_AR5211_PIMR_BNR		0x00100000
#define AR5K_AR5211_PIMR_TIM		0x00800000
#define AR5K_AR5211_PIMR_GPIO		0x01000000
#define AR5K_AR5211_PIMR_QCBRORN	0x02000000
#define AR5K_AR5211_PIMR_QCBRURN	0x04000000
#define AR5K_AR5211_PIMR_QTRIG		0x08000000

/*
 * Secondary interrupt mask registers (0 - 4)
 */
#define AR5K_AR5211_SIMR0		0x00a4
#define AR5K_AR5211_SIMR0_QCU_TXOK	0x000003ff
#define AR5K_AR5211_SIMR0_QCU_TXOK_S	0
#define AR5K_AR5211_SIMR0_QCU_TXDESC	0x03ff0000
#define AR5K_AR5211_SIMR0_QCU_TXDESC_S	16

#define AR5K_AR5211_SIMR1		0x00a8
#define AR5K_AR5211_SIMR1_QCU_TXERR	0x000003ff
#define AR5K_AR5211_SIMR1_QCU_TXERR_S	0
#define AR5K_AR5211_SIMR1_QCU_TXEOL	0x03ff0000
#define AR5K_AR5211_SIMR1_QCU_TXEOL_S	16

#define AR5K_AR5211_SIMR2		0x00ac
#define AR5K_AR5211_SIMR2_QCU_TXURN	0x000003ff
#define AR5K_AR5211_SIMR2_QCU_TXURN_S	0
#define	AR5K_AR5211_SIMR2_MCABT		0x00100000
#define	AR5K_AR5211_SIMR2_SSERR		0x00200000
#define	AR5K_AR5211_SIMR2_DPERR		0x00400000

#define AR5K_AR5211_SIMR3		0x00b0
#define AR5K_AR5211_SIMR3_QCBRORN	0x000003ff
#define AR5K_AR5211_SIMR3_QCBRORN_S	0
#define AR5K_AR5211_SIMR3_QCBRURN	0x03ff0000
#define AR5K_AR5211_SIMR3_QCBRURN_S	16

#define AR5K_AR5211_SIMR4		0x00b4
#define AR5K_AR5211_SIMR4_QTRIG		0x000003ff
#define AR5K_AR5211_SIMR4_QTRIG_S	0

/*
 * Queue control unit (QCU) registers (0 - 9)
 */
#define	AR5K_AR5211_QCU(_n, _a)		(((_n) << 2) + _a)

/*
 * QCU Transmit descriptor pointer registers
 */
#define AR5K_AR5211_QCU_TXDP(_n)	AR5K_AR5211_QCU(_n, 0x0800)

/*
 * QCU Transmit enable register
 */
#define AR5K_AR5211_QCU_TXE		0x0840

/*
 * QCU Transmit disable register
 */
#define AR5K_AR5211_QCU_TXD		0x0880

/*
 * QCU CBR configuration registers
 */
#define	AR5K_AR5211_QCU_CBRCFG(_n)		AR5K_AR5211_QCU(_n, 0x08c0)
#define	AR5K_AR5211_QCU_CBRCFG_INTVAL		0x00ffffff
#define AR5K_AR5211_QCU_CBRCFG_INTVAL_S		0
#define	AR5K_AR5211_QCU_CBRCFG_ORN_THRES	0xff000000
#define AR5K_AR5211_QCU_CBRCFG_ORN_THRES_S	24

/*
 * QCU Ready time configuration registers
 */
#define	AR5K_AR5211_QCU_RDYTIMECFG(_n)		AR5K_AR5211_QCU(_n, 0x0900)
#define	AR5K_AR5211_QCU_RDYTIMECFG_INTVAL	0x00ffffff
#define AR5K_AR5211_QCU_RDYTIMECFG_INTVAL_S	0
#define	AR5K_AR5211_QCU_RDYTIMECFG_DURATION	0x00ffffff
#define	AR5K_AR5211_QCU_RDYTIMECFG_ENABLE	0x01000000

/*
 * QCU one shot arm set registers
 */
#define	AR5K_AR5211_QCU_ONESHOTARMS(_n)	AR5K_AR5211_QCU(_n, 0x0940)
#define	AR5K_AR5211_QCU_ONESHOTARMS_M	0x0000ffff

/*
 * QCU one shot arm clear registers
 */
#define	AR5K_AR5211_QCU_ONESHOTARMC(_n)	AR5K_AR5211_QCU(_n, 0x0980)
#define	AR5K_AR5211_QCU_ONESHOTARMC_M	0x0000ffff

/*
 * QCU misc registers
 */
#define AR5K_AR5211_QCU_MISC(_n)		AR5K_AR5211_QCU(_n, 0x09c0)
#define	AR5K_AR5211_QCU_MISC_FRSHED_M		0x0000000f
#define	AR5K_AR5211_QCU_MISC_FRSHED_ASAP	0
#define	AR5K_AR5211_QCU_MISC_FRSHED_CBR		1
#define	AR5K_AR5211_QCU_MISC_FRSHED_DBA_GT	2
#define	AR5K_AR5211_QCU_MISC_FRSHED_TIM_GT	3
#define	AR5K_AR5211_QCU_MISC_FRSHED_BCN_SENT_GT	4
#define	AR5K_AR5211_QCU_MISC_ONESHOT_ENABLE	0x00000010
#define	AR5K_AR5211_QCU_MISC_CBREXP		0x00000020
#define	AR5K_AR5211_QCU_MISC_CBREXP_BCN		0x00000040
#define	AR5K_AR5211_QCU_MISC_BCN_ENABLE		0x00000080
#define	AR5K_AR5211_QCU_MISC_CBR_THRES_ENABLE	0x00000100
#define	AR5K_AR5211_QCU_MISC_TXE		0x00000200
#define	AR5K_AR5211_QCU_MISC_CBR		0x00000400
#define	AR5K_AR5211_QCU_MISC_DCU_EARLY		0x00000800

/*
 * QCU status registers
 */
#define AR5K_AR5211_QCU_STS(_n)		AR5K_AR5211_QCU(_n, 0x0a00)
#define	AR5K_AR5211_QCU_STS_FRMPENDCNT	0x00000003
#define	AR5K_AR5211_QCU_STS_CBREXPCNT	0x0000ff00

/*
 * QCU ready time shutdown register
 */
#define AR5K_AR5211_QCU_RDYTIMESHDN	0x0a40
#define AR5K_AR5211_QCU_RDYTIMESHDN_M	0x000003ff

/*
 * DCF control unit (DCU) registers (0 - 9)
 */
#define	AR5K_AR5211_DCU(_n, _a)		AR5K_AR5211_QCU(_n, _a)

/*
 * DCU QCU mask registers
 */
#define AR5K_AR5211_DCU_QCUMASK(_n)	AR5K_AR5211_DCU(_n, 0x1000)
#define AR5K_AR5211_DCU_QCUMASK_M	0x000003ff

/*
 * DCU local IFS settings register
 */
#define AR5K_AR5211_DCU_LCL_IFS(_n)		AR5K_AR5211_DCU(_n, 0x1040)
#define	AR5K_AR5211_DCU_LCL_IFS_CW_MIN		0x000003ff
#define	AR5K_AR5211_DCU_LCL_IFS_CW_MIN_S	0
#define	AR5K_AR5211_DCU_LCL_IFS_CW_MAX		0x000ffc00
#define	AR5K_AR5211_DCU_LCL_IFS_CW_MAX_S	10
#define	AR5K_AR5211_DCU_LCL_IFS_AIFS		0x0ff00000
#define	AR5K_AR5211_DCU_LCL_IFS_AIFS_S		20

/*
 * DCU retry limit registers
 */
#define AR5K_AR5211_DCU_RETRY_LMT(_n)		AR5K_AR5211_DCU(_n, 0x1080)
#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY	0x0000000f
#define AR5K_AR5211_DCU_RETRY_LMT_SH_RETRY_S	0
#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY	0x000000f0
#define AR5K_AR5211_DCU_RETRY_LMT_LG_RETRY_S	4
#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY	0x00003f00
#define AR5K_AR5211_DCU_RETRY_LMT_SSH_RETRY_S	8
#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY	0x000fc000
#define AR5K_AR5211_DCU_RETRY_LMT_SLG_RETRY_S	14

/*
 * DCU channel time registers
 */
#define AR5K_AR5211_DCU_CHAN_TIME(_n)		AR5K_AR5211_DCU(_n, 0x10c0)
#define	AR5K_AR5211_DCU_CHAN_TIME_ENABLE	0x00100000
#define	AR5K_AR5211_DCU_CHAN_TIME_DUR		0x000fffff
#define	AR5K_AR5211_DCU_CHAN_TIME_DUR_S		0

/*
 * DCU misc registers
 */
#define AR5K_AR5211_DCU_MISC(_n)		AR5K_AR5211_DCU(_n, 0x1100)
#define	AR5K_AR5211_DCU_MISC_BACKOFF		0x000007ff
#define AR5K_AR5211_DCU_MISC_BACKOFF_FRAG	0x00000200
#define	AR5K_AR5211_DCU_MISC_HCFPOLL_ENABLE	0x00000800
#define	AR5K_AR5211_DCU_MISC_BACKOFF_PERSIST	0x00001000
#define	AR5K_AR5211_DCU_MISC_FRMPRFTCH_ENABLE	0x00002000
#define	AR5K_AR5211_DCU_MISC_VIRTCOL		0x0000c000
#define	AR5K_AR5211_DCU_MISC_VIRTCOL_NORMAL	0
#define	AR5K_AR5211_DCU_MISC_VIRTCOL_MODIFIED	1
#define	AR5K_AR5211_DCU_MISC_VIRTCOL_IGNORE	2
#define	AR5K_AR5211_DCU_MISC_BCN_ENABLE		0x00010000
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_CTL	0x00060000
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_S	17
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_NONE	0
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_INTFRM	1
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_CTL_GLOBAL	2
#define	AR5K_AR5211_DCU_MISC_ARBLOCK_IGNORE	0x00080000
#define	AR5K_AR5211_DCU_MISC_SEQ_NUM_INCR_DIS	0x00100000
#define	AR5K_AR5211_DCU_MISC_POST_FR_BKOFF_DIS	0x00200000
#define	AR5K_AR5211_DCU_MISC_VIRT_COLL_POLICY	0x00400000
#define	AR5K_AR5211_DCU_MISC_BLOWN_IFS_POLICY	0x00800000
#define	AR5K_AR5211_DCU_MISC_SEQNUM_CTL		0x01000000

/*
 * DCU frame sequence number registers
 */
#define AR5K_AR5211_DCU_SEQNUM(_n)	AR5K_AR5211_DCU(_n, 0x1140)
#define	AR5K_AR5211_DCU_SEQNUM_M	0x00000fff
/*
 * DCU global IFS SIFS registers
 */
#define AR5K_AR5211_DCU_GBL_IFS_SIFS	0x1030
#define AR5K_AR5211_DCU_GBL_IFS_SIFS_M	0x0000ffff

/*
 * DCU global IFS slot interval registers
 */
#define AR5K_AR5211_DCU_GBL_IFS_SLOT	0x1070
#define AR5K_AR5211_DCU_GBL_IFS_SLOT_M	0x0000ffff

/*
 * DCU global IFS EIFS registers
 */
#define AR5K_AR5211_DCU_GBL_IFS_EIFS	0x10b0
#define AR5K_AR5211_DCU_GBL_IFS_EIFS_M	0x0000ffff

/*
 * DCU global IFS misc registers
 */
#define AR5K_AR5211_DCU_GBL_IFS_MISC			0x10f0
#define	AR5K_AR5211_DCU_GBL_IFS_MISC_LFSR_SLICE		0x00000007
#define	AR5K_AR5211_DCU_GBL_IFS_MISC_TURBO_MODE		0x00000008
#define	AR5K_AR5211_DCU_GBL_IFS_MISC_SIFS_DUR_USEC	0x000003f0
#define	AR5K_AR5211_DCU_GBL_IFS_MISC_USEC_DUR		0x000ffc00
#define	AR5K_AR5211_DCU_GBL_IFS_MISC_DCU_ARB_DELAY	0x00300000

/*
 * DCU frame prefetch control register
 */
#define AR5K_AR5211_DCU_FP		0x1230

/*
 * DCU transmit pause control/status register
 */
#define AR5K_AR5211_DCU_TXP		0x1270
#define	AR5K_AR5211_DCU_TXP_M		0x000003ff
#define	AR5K_AR5211_DCU_TXP_STATUS	0x00010000

/*
 * DCU transmit filter register
 */
#define AR5K_AR5211_DCU_TX_FILTER	0x1038

/*
 * DCU clear transmit filter register
 */
#define AR5K_AR5211_DCU_TX_FILTER_CLR	0x143c

/*
 * DCU set transmit filter register
 */
#define AR5K_AR5211_DCU_TX_FILTER_SET	0x147c