ar5212reg.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

#define AR5K_AR5212_DIAG_SW_DIS_RX		0x00000020
#define AR5K_AR5212_DIAG_SW_LOOP_BACK		0x00000040
#define AR5K_AR5212_DIAG_SW_CORR_FCS		0x00000080
#define AR5K_AR5212_DIAG_SW_CHAN_INFO		0x00000100
#define AR5K_AR5212_DIAG_SW_EN_SCRAM_SEED	0x00000200
#define AR5K_AR5212_DIAG_SW_ECO_ENABLE		0x00000400
#define AR5K_AR5212_DIAG_SW_SCRAM_SEED_M	0x0001fc00
#define AR5K_AR5212_DIAG_SW_SCRAM_SEED_S	10
#define AR5K_AR5212_DIAG_SW_FRAME_NV0		0x00020000
#define AR5K_AR5212_DIAG_SW_OBSPT_M		0x000c0000
#define AR5K_AR5212_DIAG_SW_OBSPT_S		18

/*
 * TSF (clock) register (lower 32 bits)
 */
#define AR5K_AR5212_TSF_L32	0x804c

/*
 * TSF (clock) register (higher 32 bits)
 */
#define AR5K_AR5212_TSF_U32	0x8050

/*
 * ADDAC test register
 */
#define AR5K_AR5212_ADDAC_TEST	0x8054

/*
 * Default antenna register
 */
#define AR5K_AR5212_DEFAULT_ANTENNA	0x8058

/*
 * Last beacon timestamp register
 */
#define AR5K_AR5212_LAST_TSTP	0x8080

/*
 * NAV register (current)
 */
#define AR5K_AR5212_NAV		0x8084

/*
 * RTS success register
 */
#define AR5K_AR5212_RTS_OK	0x8088

/*
 * RTS failure register
 */
#define AR5K_AR5212_RTS_FAIL	0x808c

/*
 * ACK failure register
 */
#define AR5K_AR5212_ACK_FAIL	0x8090

/*
 * FCS failure register
 */
#define AR5K_AR5212_FCS_FAIL	0x8094

/*
 * Beacon count register
 */
#define AR5K_AR5212_BEACON_CNT	0x8098

/*
 * XR (eXtended Range) mode register
 */
#define AR5K_AR5212_XRMODE			0x80c0
#define	AR5K_AR5212_XRMODE_POLL_TYPE_M		0x0000003f
#define	AR5K_AR5212_XRMODE_POLL_TYPE_S		0
#define	AR5K_AR5212_XRMODE_POLL_SUBTYPE_M	0x0000003c
#define	AR5K_AR5212_XRMODE_POLL_SUBTYPE_S	2
#define	AR5K_AR5212_XRMODE_POLL_WAIT_ALL	0x00000080
#define	AR5K_AR5212_XRMODE_SIFS_DELAY		0x000fff00
#define	AR5K_AR5212_XRMODE_FRAME_HOLD_M		0xfff00000
#define	AR5K_AR5212_XRMODE_FRAME_HOLD_S		20

/*
 * XR delay register
 */
#define AR5K_AR5212_XRDELAY			0x80c4
#define AR5K_AR5212_XRDELAY_SLOT_DELAY_M	0x0000ffff
#define AR5K_AR5212_XRDELAY_SLOT_DELAY_S	0
#define AR5K_AR5212_XRDELAY_CHIRP_DELAY_M	0xffff0000
#define AR5K_AR5212_XRDELAY_CHIRP_DELAY_S	16

/*
 * XR timeout register
 */
#define AR5K_AR5212_XRTIMEOUT		0x80c8
#define AR5K_AR5212_XRTIMEOUT_CHIRP_M	0x0000ffff
#define AR5K_AR5212_XRTIMEOUT_CHIRP_S	0
#define AR5K_AR5212_XRTIMEOUT_POLL_M	0xffff0000
#define AR5K_AR5212_XRTIMEOUT_POLL_S	16

/*
 * XR chirp register
 */
#define AR5K_AR5212_XRCHIRP		0x80cc
#define AR5K_AR5212_XRCHIRP_SEND	0x00000001
#define AR5K_AR5212_XRCHIRP_GAP		0xffff0000

/*
 * XR stomp register
 */
#define AR5K_AR5212_XRSTOMP		0x80d0
#define AR5K_AR5212_XRSTOMP_TX		0x00000001
#define AR5K_AR5212_XRSTOMP_RX_ABORT	0x00000002
#define AR5K_AR5212_XRSTOMP_RSSI_THRES	0x0000ff00

/*
 * First enhanced sleep register
 */
#define AR5K_AR5212_SLEEP0		0x80d4
#define AR5K_AR5212_SLEEP0_NEXT_DTIM	0x0007ffff
#define AR5K_AR5212_SLEEP0_NEXT_DTIM_S	0
#define AR5K_AR5212_SLEEP0_ASSUME_DTIM	0x00080000
#define AR5K_AR5212_SLEEP0_ENH_SLEEP_EN	0x00100000
#define AR5K_AR5212_SLEEP0_CABTO	0xff000000
#define AR5K_AR5212_SLEEP0_CABTO_S	24

/*
 * Second enhanced sleep register
 */
#define AR5K_AR5212_SLEEP1		0x80d8
#define AR5K_AR5212_SLEEP1_NEXT_TIM	0x0007ffff
#define AR5K_AR5212_SLEEP1_NEXT_TIM_S	0
#define AR5K_AR5212_SLEEP1_BEACON_TO	0xff000000
#define AR5K_AR5212_SLEEP1_BEACON_TO_S	24

/*
 * Third enhanced sleep register
 */
#define AR5K_AR5212_SLEEP2		0x80dc
#define AR5K_AR5212_SLEEP2_TIM_PER	0x0000ffff
#define AR5K_AR5212_SLEEP2_TIM_PER_S	0
#define AR5K_AR5212_SLEEP2_DTIM_PER	0xffff0000
#define AR5K_AR5212_SLEEP2_DTIM_PER_S	16

/*
 * BSSID mask registers
 */
#define AR5K_AR5212_BSS_IDM0	0x80e0
#define AR5K_AR5212_BSS_IDM1	0x80e4

/*
 * TX power control (TPC) register
 */
#define AR5K_AR5212_TXPC		0x80e8
#define AR5K_AR5212_TXPC_ACK_M		0x0000003f
#define AR5K_AR5212_TXPC_ACK_S		0
#define AR5K_AR5212_TXPC_CTS_M		0x00003f00
#define AR5K_AR5212_TXPC_CTS_S		8
#define AR5K_AR5212_TXPC_CHIRP_M	0x003f0000
#define AR5K_AR5212_TXPC_CHIRP_S	22

/*
 * Profile count registers
 */
#define AR5K_AR5212_PROFCNT_TX		0x80ec
#define AR5K_AR5212_PROFCNT_RX		0x80f0
#define AR5K_AR5212_PROFCNT_RXCLR	0x80f4
#define AR5K_AR5212_PROFCNT_CYCLE	0x80f8

/*
 * TSF parameter register
 */
#define AR5K_AR5212_TSF_PARM		0x8104
#define AR5K_AR5212_TSF_PARM_INC_M	0x000000ff
#define AR5K_AR5212_TSF_PARM_INC_S	0

/*
 * PHY error filter register
 */
#define AR5K_AR5212_PHY_ERR_FIL		0x810c
#define AR5K_AR5212_PHY_ERR_FIL_RADAR	0x00000020
#define AR5K_AR5212_PHY_ERR_FIL_OFDM	0x00020000
#define AR5K_AR5212_PHY_ERR_FIL_CCK	0x02000000

/*
 * Rate duration register
 */
#define AR5K_AR5212_RATE_DUR_0		0x8700
#define AR5K_AR5212_RATE_DUR(_n)	(AR5K_AR5212_RATE_DUR_0 + ((_n) << 2))

/*
 * Key table (WEP) register
 */
#define AR5K_AR5212_KEYTABLE_0		0x8800
#define AR5K_AR5212_KEYTABLE(_n)	(AR5K_AR5212_KEYTABLE_0 + ((_n) << 5))
#define AR5K_AR5212_KEYTABLE_OFF(_n, x)	(AR5K_AR5212_KEYTABLE(_n) + (x << 2))
#define AR5K_AR5212_KEYTABLE_TYPE(_n)	AR5K_AR5212_KEYTABLE_OFF(_n, 5)
#define AR5K_AR5212_KEYTABLE_TYPE_40	0x00000000
#define AR5K_AR5212_KEYTABLE_TYPE_104	0x00000001
#define AR5K_AR5212_KEYTABLE_TYPE_128	0x00000003
#define AR5K_AR5212_KEYTABLE_TYPE_TKIP	0x00000004
#define AR5K_AR5212_KEYTABLE_TYPE_AES	0x00000005
#define AR5K_AR5212_KEYTABLE_TYPE_CCM	0x00000006
#define AR5K_AR5212_KEYTABLE_TYPE_NULL	0x00000007
#define AR5K_AR5212_KEYTABLE_ANTENNA	0x00000008
#define AR5K_AR5212_KEYTABLE_MAC0(_n)	AR5K_AR5212_KEYTABLE_OFF(_n, 6)
#define AR5K_AR5212_KEYTABLE_MAC1(_n)	AR5K_AR5212_KEYTABLE_OFF(_n, 7)
#define AR5K_AR5212_KEYTABLE_VALID	0x00008000

#define AR5K_AR5212_KEYTABLE_SIZE	128
#define AR5K_AR5212_KEYCACHE_SIZE	8

/*
 * PHY register
 */
#define	AR5K_AR5212_PHY(_n)		(0x9800 + ((_n) << 2))
#define AR5K_AR5212_PHY_SHIFT_2GHZ	0x00004007
#define AR5K_AR5212_PHY_SHIFT_5GHZ	0x00000007

/*
 * PHY turbo mode register
 */
#define	AR5K_AR5212_PHY_TURBO		0x9804
#define	AR5K_AR5212_PHY_TURBO_MODE	0x00000001
#define	AR5K_AR5212_PHY_TURBO_SHORT	0x00000002

/*
 * PHY agility command register
 */
#define	AR5K_AR5212_PHY_AGC		0x9808
#define	AR5K_AR5212_PHY_AGC_DISABLE	0x08000000

/*
 * PHY timing register
 */
#define	AR5K_AR5212_PHY_TIMING_3		0x9814
#define	AR5K_AR5212_PHY_TIMING_3_DSC_MAN	0xfffe0000
#define	AR5K_AR5212_PHY_TIMING_3_DSC_MAN_S	17
#define	AR5K_AR5212_PHY_TIMING_3_DSC_EXP	0x0001e000
#define	AR5K_AR5212_PHY_TIMING_3_DSC_EXP_S	13

/*
 * PHY chip revision register
 */
#define	AR5K_AR5212_PHY_CHIP_ID		0x9818

/*
 * PHY activation register
 */
#define	AR5K_AR5212_PHY_ACTIVE		0x981c
#define	AR5K_AR5212_PHY_ENABLE		0x00000001
#define	AR5K_AR5212_PHY_DISABLE		0x00000002

/*
 * PHY agility control register
 */
#define	AR5K_AR5212_PHY_AGCCTL		0x9860
#define	AR5K_AR5212_PHY_AGCCTL_CAL	0x00000001
#define	AR5K_AR5212_PHY_AGCCTL_NF	0x00000002

/*
 * PHY noise floor status register
 */
#define AR5K_AR5212_PHY_NF		0x9864
#define AR5K_AR5212_PHY_NF_M		0x000001ff
#define AR5K_AR5212_PHY_NF_ACTIVE	0x00000100
#define AR5K_AR5212_PHY_NF_RVAL(_n)	(((_n) >> 19) & AR5K_AR5212_PHY_NF_M)
#define AR5K_AR5212_PHY_NF_AVAL(_n)	(-((_n) ^ AR5K_AR5212_PHY_NF_M) + 1)
#define AR5K_AR5212_PHY_NF_SVAL(_n)	(((_n) & AR5K_AR5212_PHY_NF_M) | (1 << 9))

/*
 * PHY sleep registers
 */
#define AR5K_AR5212_PHY_SCR		0x9870
#define AR5K_AR5212_PHY_SCR_32MHZ	0x0000001f
#define AR5K_AR5212_PHY_SLMT		0x9874
#define AR5K_AR5212_PHY_SLMT_32MHZ	0x0000007f
#define AR5K_AR5212_PHY_SCAL		0x9878
#define AR5K_AR5212_PHY_SCAL_32MHZ	0x0000000e

/*
 * PHY PLL control register
 */
#define	AR5K_AR5212_PHY_PLL		0x987c
#define	AR5K_AR5212_PHY_PLL_40MHZ	0x000000aa
#define	AR5K_AR5212_PHY_PLL_44MHZ	0x000000ab
#define AR5K_AR5212_PHY_PLL_AR5111	0x00000000
#define AR5K_AR5212_PHY_PLL_AR5112	0x00000040

/*
 * PHY receiver delay register
 */
#define	AR5K_AR5212_PHY_RX_DELAY	0x9914
#define	AR5K_AR5212_PHY_RX_DELAY_M	0x00003fff

/*
 * PHY timing IQ control register
 */
#define	AR5K_AR5212_PHY_IQ			0x9920
#define	AR5K_AR5212_PHY_IQ_CORR_Q_Q_COFF	0x0000001f
#define	AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF	0x000007e0
#define	AR5K_AR5212_PHY_IQ_CORR_Q_I_COFF_S	5
#define	AR5K_AR5212_PHY_IQ_CORR_ENABLE		0x00000800
#define	AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX	0x0000f000
#define	AR5K_AR5212_PHY_IQ_CAL_NUM_LOG_MAX_S	12
#define	AR5K_AR5212_PHY_IQ_RUN			0x00010000

/*
 * PHY PAPD probe register
 */
#define	AR5K_AR5212_PHY_PAPD_PROBE		0x9930
#define	AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER	0x00007e00
#define	AR5K_AR5212_PHY_PAPD_PROBE_TXPOWER_S	9
#define	AR5K_AR5212_PHY_PAPD_PROBE_TX_NEXT	0x00008000
#define	AR5K_AR5212_PHY_PAPD_PROBE_TYPE		0x01800000
#define	AR5K_AR5212_PHY_PAPD_PROBE_TYPE_S	23
#define	AR5K_AR5212_PHY_PAPD_PROBE_TYPE_OFDM	0
#define	AR5K_AR5212_PHY_PAPD_PROBE_TYPE_XR	1
#define	AR5K_AR5212_PHY_PAPD_PROBE_TYPE_CCK	2
#define	AR5K_AR5212_PHY_PAPD_PROBE_GAINF	0xfe000000
#define	AR5K_AR5212_PHY_PAPD_PROBE_GAINF_S	25

/*
 * PHY TX power registers
 */
#define	AR5K_AR5212_PHY_TXPOWER_RATE1			0x9934
#define	AR5K_AR5212_PHY_TXPOWER_RATE2			0x9938
#define	AR5K_AR5212_PHY_TXPOWER_RATE_MAX		0x993c
#define	AR5K_AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE	0x00000040
#define	AR5K_AR5212_PHY_TXPOWER_RATE3			0xa234
#define	AR5K_AR5212_PHY_TXPOWER_RATE4			0xa238

/*
 * PHY frame control register
 */
#define	AR5K_AR5212_PHY_FC		0x9944
#define	AR5K_AR5212_PHY_FC_TX_CLIP	0x00000038
#define	AR5K_AR5212_PHY_FC_TX_CLIP_S	3

/*
 * PHY radar detection enable register
 */
#define	AR5K_AR5212_PHY_RADAR		0x9954
#define	AR5K_AR5212_PHY_RADAR_DISABLE	0x00000000
#define	AR5K_AR5212_PHY_RADAR_ENABLE	0x00000001

/*
 * PHY antenna switch table registers
 */
#define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_0	0x9960
#define AR5K_AR5212_PHY_ANT_SWITCH_TABLE_1	0x9964

/*
 * PHY clock sleep registers
 */
#define AR5K_AR5212_PHY_SCLOCK		0x99f0
#define AR5K_AR5212_PHY_SCLOCK_32MHZ	0x0000000c
#define AR5K_AR5212_PHY_SDELAY		0x99f4
#define AR5K_AR5212_PHY_SDELAY_32MHZ	0x000000ff
#define AR5K_AR5212_PHY_SPENDING	0x99f8
#define AR5K_AR5212_PHY_SPENDING_AR5111	0x00000018
#define AR5K_AR5212_PHY_SPENDING_AR5112	0x00000014

/*
 * PHY timing IQ calibration result register
 */
#define	AR5K_AR5212_PHY_IQRES_CAL_PWR_I	0x9c10
#define	AR5K_AR5212_PHY_IQRES_CAL_PWR_Q	0x9c14
#define	AR5K_AR5212_PHY_IQRES_CAL_CORR	0x9c18

/*
 * PHY current RSSI register
 */
#define	AR5K_AR5212_PHY_CURRENT_RSSI	0x9c1c

/*
 * PHY PCDAC TX power register
 */
#define	AR5K_AR5212_PHY_PCDAC_TXPOWER(_n)	(0xa180 + ((_n) << 2))

/*
 * PHY mode register
 */
#define	AR5K_AR5212_PHY_MODE		0x0a200
#define	AR5K_AR5212_PHY_MODE_MOD	0x00000001
#define AR5K_AR5212_PHY_MODE_MOD_OFDM	0
#define AR5K_AR5212_PHY_MODE_MOD_CCK	1
#define AR5K_AR5212_PHY_MODE_FREQ	0x00000002
#define	AR5K_AR5212_PHY_MODE_FREQ_5GHZ	0
#define	AR5K_AR5212_PHY_MODE_FREQ_2GHZ	2
#define AR5K_AR5212_PHY_MODE_MOD_DYN	0x00000004
#define AR5K_AR5212_PHY_MODE_RAD	0x00000008
#define AR5K_AR5212_PHY_MODE_RAD_AR5111	0
#define AR5K_AR5212_PHY_MODE_RAD_AR5112	8
#define AR5K_AR5212_PHY_MODE_XR		0x00000010

/*
 * PHY CCK transmit control register
 */
#define AR5K_AR5212_PHY_CCKTXCTL        0xa204
#define AR5K_AR5212_PHY_CCKTXCTL_WORLD  0x00000000
#define AR5K_AR5212_PHY_CCKTXCTL_JAPAN  0x00000010
 	 
/*
 * PHY 2GHz gain register
 */
#define	AR5K_AR5212_PHY_GAIN_2GHZ		0xa20c
#define	AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX	0x00fc0000
#define	AR5K_AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX_S	18

#endif