ar5212reg.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

 */
#define	AR5K_AR5212_DCU(_n, _a)		AR5K_AR5212_QCU(_n, _a)

/*
 * DCU QCU mask registers
 */
#define AR5K_AR5212_DCU_QCUMASK(_n)	AR5K_AR5212_DCU(_n, 0x1000)
#define AR5K_AR5212_DCU_QCUMASK_M	0x000003ff

/*
 * DCU local IFS settings register
 */
#define AR5K_AR5212_DCU_LCL_IFS(_n)		AR5K_AR5212_DCU(_n, 0x1040)
#define	AR5K_AR5212_DCU_LCL_IFS_CW_MIN	        0x000003ff
#define	AR5K_AR5212_DCU_LCL_IFS_CW_MIN_S	0
#define	AR5K_AR5212_DCU_LCL_IFS_CW_MAX	        0x000ffc00
#define	AR5K_AR5212_DCU_LCL_IFS_CW_MAX_S	10
#define	AR5K_AR5212_DCU_LCL_IFS_AIFS		0x0ff00000
#define	AR5K_AR5212_DCU_LCL_IFS_AIFS_S		20

/*
 * DCU retry limit registers
 */
#define AR5K_AR5212_DCU_RETRY_LMT(_n)		AR5K_AR5212_DCU(_n, 0x1080)
#define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY	0x0000000f
#define AR5K_AR5212_DCU_RETRY_LMT_SH_RETRY_S	0
#define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY	0x000000f0
#define AR5K_AR5212_DCU_RETRY_LMT_LG_RETRY_S	4
#define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY	0x00003f00
#define AR5K_AR5212_DCU_RETRY_LMT_SSH_RETRY_S	8
#define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY	0x000fc000
#define AR5K_AR5212_DCU_RETRY_LMT_SLG_RETRY_S	14

/*
 * DCU channel time registers
 */
#define AR5K_AR5212_DCU_CHAN_TIME(_n)		AR5K_AR5212_DCU(_n, 0x10c0)
#define	AR5K_AR5212_DCU_CHAN_TIME_DUR		0x000fffff
#define	AR5K_AR5212_DCU_CHAN_TIME_DUR_S		0
#define	AR5K_AR5212_DCU_CHAN_TIME_ENABLE	0x00100000

/*
 * DCU misc registers
 */
#define AR5K_AR5212_DCU_MISC(_n)		AR5K_AR5212_DCU(_n, 0x1100)
#define	AR5K_AR5212_DCU_MISC_BACKOFF		0x000007ff
#define AR5K_AR5212_DCU_MISC_BACKOFF_FRAG	0x00000200
#define	AR5K_AR5212_DCU_MISC_HCFPOLL_ENABLE	0x00000800
#define	AR5K_AR5212_DCU_MISC_BACKOFF_PERSIST	0x00001000
#define	AR5K_AR5212_DCU_MISC_FRMPRFTCH_ENABLE	0x00002000
#define	AR5K_AR5212_DCU_MISC_VIRTCOL		0x0000c000
#define	AR5K_AR5212_DCU_MISC_VIRTCOL_NORMAL	0
#define	AR5K_AR5212_DCU_MISC_VIRTCOL_MODIFIED	1
#define	AR5K_AR5212_DCU_MISC_VIRTCOL_IGNORE	2
#define	AR5K_AR5212_DCU_MISC_BCN_ENABLE		0x00010000
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_CTL	0x00060000
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_S	17
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_NONE	0
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_INTFRM	1
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL	2
#define	AR5K_AR5212_DCU_MISC_ARBLOCK_IGNORE	0x00080000
#define	AR5K_AR5212_DCU_MISC_SEQ_NUM_INCR_DIS	0x00100000
#define	AR5K_AR5212_DCU_MISC_POST_FR_BKOFF_DIS	0x00200000
#define	AR5K_AR5212_DCU_MISC_VIRT_COLL_POLICY	0x00400000
#define	AR5K_AR5212_DCU_MISC_BLOWN_IFS_POLICY	0x00800000
#define	AR5K_AR5212_DCU_MISC_SEQNUM_CTL		0x01000000

/*
 * DCU frame sequence number registers
 */
#define AR5K_AR5212_DCU_SEQNUM(_n)	AR5K_AR5212_DCU(_n, 0x1140)
#define	AR5K_AR5212_DCU_SEQNUM_M	0x00000fff
/*
 * DCU global IFS SIFS registers
 */
#define AR5K_AR5212_DCU_GBL_IFS_SIFS	0x1030
#define AR5K_AR5212_DCU_GBL_IFS_SIFS_M	0x0000ffff

/*
 * DCU global IFS slot interval registers
 */
#define AR5K_AR5212_DCU_GBL_IFS_SLOT	0x1070
#define AR5K_AR5212_DCU_GBL_IFS_SLOT_M	0x0000ffff

/*
 * DCU global IFS EIFS registers
 */
#define AR5K_AR5212_DCU_GBL_IFS_EIFS	0x10b0
#define AR5K_AR5212_DCU_GBL_IFS_EIFS_M	0x0000ffff

/*
 * DCU global IFS misc registers
 */
#define AR5K_AR5212_DCU_GBL_IFS_MISC			0x10f0
#define	AR5K_AR5212_DCU_GBL_IFS_MISC_LFSR_SLICE		0x00000007
#define	AR5K_AR5212_DCU_GBL_IFS_MISC_TURBO_MODE		0x00000008
#define	AR5K_AR5212_DCU_GBL_IFS_MISC_SIFS_DUR_USEC	0x000003f0
#define	AR5K_AR5212_DCU_GBL_IFS_MISC_USEC_DUR		0x000ffc00
#define	AR5K_AR5212_DCU_GBL_IFS_MISC_DCU_ARB_DELAY	0x00300000

/*
 * DCU frame prefetch control register
 */
#define AR5K_AR5212_DCU_FP		0x1230

/*
 * DCU transmit pause control/status register
 */
#define AR5K_AR5212_DCU_TXP		0x1270
#define	AR5K_AR5212_DCU_TXP_M		0x000003ff
#define	AR5K_AR5212_DCU_TXP_STATUS	0x00010000

/*
 * DCU transmit filter register
 */
#define AR5K_AR5212_DCU_TX_FILTER	0x1038

/*
 * DCU clear transmit filter register
 */
#define AR5K_AR5212_DCU_TX_FILTER_CLR	0x143c

/*
 * DCU set transmit filter register
 */
#define AR5K_AR5212_DCU_TX_FILTER_SET	0x147c

/*
 * DMA size definitions
 */
typedef enum {
	AR5K_AR5212_DMASIZE_4B = 0,
	AR5K_AR5212_DMASIZE_8B = 1,
	AR5K_AR5212_DMASIZE_16B = 2,
	AR5K_AR5212_DMASIZE_32B = 3,
	AR5K_AR5212_DMASIZE_64B = 4,
	AR5K_AR5212_DMASIZE_128B = 5,
	AR5K_AR5212_DMASIZE_256B = 6,
	AR5K_AR5212_DMASIZE_512B = 7
} ar5k_ar5212_dmasize_t;

/*
 * Reset control register
 */
#define AR5K_AR5212_RC			0x4000
#define AR5K_AR5212_RC_PCU		0x00000001
#define AR5K_AR5212_RC_BB		0x00000002
#define AR5K_AR5212_RC_PCI		0x00000010
#define AR5K_AR5212_RC_CHIP		(				\
	AR5K_AR5212_RC_PCU | AR5K_AR5212_RC_BB | AR5K_AR5212_RC_PCI	\
)

/*
 * Sleep control register
 */
#define AR5K_AR5212_SCR			0x4004
#define AR5K_AR5212_SCR_SLDUR		0x0000ffff
#define AR5K_AR5212_SCR_SLE		0x00030000
#define AR5K_AR5212_SCR_SLE_S		16
#define AR5K_AR5212_SCR_SLE_WAKE	0x00000000
#define AR5K_AR5212_SCR_SLE_SLP		0x00010000
#define AR5K_AR5212_SCR_SLE_ALLOW	0x00020000
#define AR5K_AR5212_SCR_SLE_UNITS	0x00000008

/*
 * Interrupt pending register
 */
#define AR5K_AR5212_INTPEND	0x4008
#define AR5K_AR5212_INTPEND_M	0x00000001

/*
 * Sleep force register
 */
#define AR5K_AR5212_SFR		0x400c
#define AR5K_AR5212_SFR_M	0x00000001

/*
 * PCI configuration register
 */
#define AR5K_AR5212_PCICFG		0x4010
#define AR5K_AR5212_PCICFG_CLKRUNEN	0x00000004
#define AR5K_AR5212_PCICFG_EESIZE	0x00000018
#define AR5K_AR5212_PCICFG_EESIZE_S	3
#define AR5K_AR5212_PCICFG_EESIZE_4K	0
#define AR5K_AR5212_PCICFG_EESIZE_8K	1
#define AR5K_AR5212_PCICFG_EESIZE_16K	2
#define AR5K_AR5212_PCICFG_EESIZE_FAIL	3
#define AR5K_AR5212_PCICFG_LED		0x00000060
#define AR5K_AR5212_PCICFG_LED_NONE	0x00000000
#define AR5K_AR5212_PCICFG_LED_PEND	0x00000020
#define AR5K_AR5212_PCICFG_LED_ASSOC	0x00000040
#define	AR5K_AR5212_PCICFG_BUS_SEL	0x00000380
#define	AR5K_AR5212_PCICFG_CBEFIX_DIS	0x00000400
#define AR5K_AR5212_PCICFG_SL_INTEN	0x00000800
#define AR5K_AR5212_PCICFG_SL_INPEN	0x00002800
#define AR5K_AR5212_PCICFG_SPWR_DN	0x00010000
#define AR5K_AR5212_PCICFG_LEDMODE	0x000e0000
#define AR5K_AR5212_PCICFG_LEDMODE_PROP	0x00000000
#define AR5K_AR5212_PCICFG_LEDMODE_PROM	0x00020000
#define AR5K_AR5212_PCICFG_LEDMODE_PWR	0x00040000
#define AR5K_AR5212_PCICFG_LEDMODE_RAND	0x00060000
#define AR5K_AR5212_PCICFG_LEDBLINK	0x00700000
#define AR5K_AR5212_PCICFG_LEDBLINK_S	20
#define AR5K_AR5212_PCICFG_LEDSLOW	0x00800000
#define AR5K_AR5212_PCICFG_LEDSTATE					\
	(AR5K_AR5212_PCICFG_LED | AR5K_AR5212_PCICFG_LEDMODE |		\
	AR5K_AR5212_PCICFG_LEDBLINK | AR5K_AR5212_PCICFG_LEDSLOW)

/*
 * "General Purpose Input/Output" (GPIO) control register
 */
#define AR5K_AR5212_GPIOCR		0x4014
#define AR5K_AR5212_GPIOCR_INT_ENA	0x00008000
#define AR5K_AR5212_GPIOCR_INT_SELL	0x00000000
#define AR5K_AR5212_GPIOCR_INT_SELH	0x00010000
#define AR5K_AR5212_GPIOCR_NONE(n)	(0 << ((n) * 2))
#define AR5K_AR5212_GPIOCR_OUT0(n)	(1 << ((n) * 2))
#define AR5K_AR5212_GPIOCR_OUT1(n)	(2 << ((n) * 2))
#define AR5K_AR5212_GPIOCR_ALL(n)	(3 << ((n) * 2))
#define AR5K_AR5212_GPIOCR_INT_SEL(n)	((n) << 12)

#define AR5K_AR5212_NUM_GPIO	6

/*
 * "General Purpose Input/Output" (GPIO) data output register
 */
#define AR5K_AR5212_GPIODO	0x4018

/*
 * "General Purpose Input/Output" (GPIO) data input register
 */
#define AR5K_AR5212_GPIODI	0x401c
#define AR5K_AR5212_GPIODI_M	0x0000002f

/*
 * Silicon revision register
 */
#define AR5K_AR5212_SREV		0x4020
#define AR5K_AR5212_SREV_REV		0x0000000f
#define AR5K_AR5212_SREV_REV_S		0
#define AR5K_AR5212_SREV_VER		0x000000ff
#define AR5K_AR5212_SREV_VER_S		4

/*
 * EEPROM access registers
 */
#define AR5K_AR5212_EEPROM_BASE		0x6000
#define AR5K_AR5212_EEPROM_DATA		0x6004
#define AR5K_AR5212_EEPROM_CMD		0x6008
#define AR5K_AR5212_EEPROM_CMD_READ	0x00000001
#define AR5K_AR5212_EEPROM_CMD_WRITE	0x00000002
#define AR5K_AR5212_EEPROM_CMD_RESET	0x00000004
#define AR5K_AR5212_EEPROM_STATUS	0x600c
#define AR5K_AR5212_EEPROM_STAT_RDERR	0x00000001
#define AR5K_AR5212_EEPROM_STAT_RDDONE	0x00000002
#define AR5K_AR5212_EEPROM_STAT_WRERR	0x00000004
#define AR5K_AR5212_EEPROM_STAT_WRDONE	0x00000008
#define AR5K_AR5212_EEPROM_CFG		0x6010

/*
 * PCU registers
 */

#define AR5K_AR5212_PCU_MIN	0x8000
#define AR5K_AR5212_PCU_MAX	0x8fff

/*
 * First station id register (MAC address in lower 32 bits)
 */
#define AR5K_AR5212_STA_ID0	0x8000

/*
 * Second station id register (MAC address in upper 16 bits)
 */
#define AR5K_AR5212_STA_ID1			0x8004
#define AR5K_AR5212_STA_ID1_AP			0x00010000
#define AR5K_AR5212_STA_ID1_ADHOC		0x00020000
#define AR5K_AR5212_STA_ID1_PWR_SV		0x00040000
#define AR5K_AR5212_STA_ID1_NO_KEYSRCH		0x00080000
#define AR5K_AR5212_STA_ID1_PCF			0x00100000
#define AR5K_AR5212_STA_ID1_DEFAULT_ANTENNA	0x00200000
#define AR5K_AR5212_STA_ID1_DESC_ANTENNA	0x00400000
#define AR5K_AR5212_STA_ID1_RTS_DEFAULT_ANTENNA	0x00800000
#define AR5K_AR5212_STA_ID1_ACKCTS_6MB		0x01000000
#define AR5K_AR5212_STA_ID1_BASE_RATE_11B	0x02000000

/*
 * First BSSID register (MAC address, lower 32bits)
 */
#define AR5K_AR5212_BSS_ID0	0x8008

/*
 * Second BSSID register (MAC address in upper 16 bits)
 *
 * AID: Association ID
 */
#define AR5K_AR5212_BSS_ID1		0x800c
#define AR5K_AR5212_BSS_ID1_AID		0xffff0000
#define AR5K_AR5212_BSS_ID1_AID_S	16

/*
 * Backoff slot time register
 */
#define AR5K_AR5212_SLOT_TIME	0x8010

/*
 * ACK/CTS timeout register
 */
#define AR5K_AR5212_TIME_OUT		0x8014
#define AR5K_AR5212_TIME_OUT_ACK	0x00001fff
#define AR5K_AR5212_TIME_OUT_ACK_S	0
#define AR5K_AR5212_TIME_OUT_CTS	0x1fff0000
#define AR5K_AR5212_TIME_OUT_CTS_S	16

/*
 * RSSI threshold register
 */
#define AR5K_AR5212_RSSI_THR		0x8018
#define AR5K_AR5212_RSSI_THR_M		0x000000ff
#define AR5K_AR5212_RSSI_THR_BMISS	0x0000ff00
#define AR5K_AR5212_RSSI_THR_BMISS_S	8

/*
 * Transmit latency register
 */
#define AR5K_AR5212_USEC		0x801c
#define AR5K_AR5212_USEC_1		0x0000007f
#define AR5K_AR5212_USEC_1_S		0
#define AR5K_AR5212_USEC_32		0x00003f80
#define AR5K_AR5212_USEC_32_S		7
#define AR5K_AR5212_USEC_TX_LATENCY	0x007fc000
#define AR5K_AR5212_USEC_TX_LATENCY_S	14
#define AR5K_AR5212_USEC_RX_LATENCY	0x1f800000
#define AR5K_AR5212_USEC_RX_LATENCY_S	23
#define AR5K_AR5311_USEC_TX_LATENCY	0x000fc000
#define AR5K_AR5311_USEC_TX_LATENCY_S	14
#define AR5K_AR5311_USEC_RX_LATENCY	0x03f00000
#define AR5K_AR5311_USEC_RX_LATENCY_S	20

/*
 * PCU beacon control register
 */
#define AR5K_AR5212_BEACON		0x8020
#define AR5K_AR5212_BEACON_PERIOD	0x0000ffff
#define AR5K_AR5212_BEACON_PERIOD_S	0
#define AR5K_AR5212_BEACON_TIM		0x007f0000
#define AR5K_AR5212_BEACON_TIM_S	16
#define AR5K_AR5212_BEACON_ENABLE	0x00800000
#define AR5K_AR5212_BEACON_RESET_TSF	0x01000000

/*
 * CFP period register
 */
#define AR5K_AR5212_CFP_PERIOD		0x8024

/*
 * Next beacon time register
 */
#define AR5K_AR5212_TIMER0		0x8028

/*
 * Next DMA beacon alert register
 */
#define AR5K_AR5212_TIMER1		0x802c

/*
 * Next software beacon alert register
 */
#define AR5K_AR5212_TIMER2		0x8030

/*
 * Next ATIM window time register
 */
#define AR5K_AR5212_TIMER3		0x8034

/*
 * CFP duration register
 */
#define AR5K_AR5212_CFP_DUR		0x8038

/*
 * Receive filter register
 */
#define AR5K_AR5212_RX_FILTER		0x803c
#define AR5K_AR5212_RX_FILTER_UNICAST	0x00000001
#define AR5K_AR5212_RX_FILTER_MULTICAST	0x00000002
#define AR5K_AR5212_RX_FILTER_BROADCAST	0x00000004
#define AR5K_AR5212_RX_FILTER_CONTROL	0x00000008
#define AR5K_AR5212_RX_FILTER_BEACON	0x00000010
#define AR5K_AR5212_RX_FILTER_PROMISC	0x00000020
#define AR5K_AR5212_RX_FILTER_XR_POLL	0x00000040
#define AR5K_AR5212_RX_FILTER_PROBE_REQ	0x00000080

/*
 * Multicast filter register (lower 32 bits)
 */
#define AR5K_AR5212_MCAST_FIL0	0x8040

/*
 * Multicast filter register (higher 16 bits)
 */
#define AR5K_AR5212_MCAST_FIL1	0x8044

/*
 * PCU control register
 */
#define AR5K_AR5212_DIAG_SW			0x8048
#define AR5K_AR5212_DIAG_SW_DIS_WEP_ACK		0x00000001
#define AR5K_AR5212_DIAG_SW_DIS_ACK		0x00000002
#define AR5K_AR5212_DIAG_SW_DIS_CTS		0x00000004
#define AR5K_AR5212_DIAG_SW_DIS_ENC		0x00000008
#define AR5K_AR5212_DIAG_SW_DIS_DEC		0x00000010