ar5212reg.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

/*	$OpenBSD: ar5212reg.h,v 1.7 2005/12/18 17:59:58 reyk Exp $	*/

/*
 * Copyright (c) 2004, 2005 Reyk Floeter <[e-mail]>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Known registers of the Atheros AR5001 Wireless LAN chipsets
 * (AR5212/AR5311).
 */

#ifndef _AR5K_AR5212_REG_H
#define _AR5K_AR5212_REG_H

/*
 * Command register
 */
#define AR5K_AR5212_CR		0x0008
#define AR5K_AR5212_CR_RXE	0x00000004
#define AR5K_AR5212_CR_RXD	0x00000020
#define AR5K_AR5212_CR_SWI	0x00000040

/*
 * Receive queue descriptor pointer register
 */
#define AR5K_AR5212_RXDP	0x000c

/*
 * Configuration and status register
 */
#define AR5K_AR5212_CFG			0x0014
#define AR5K_AR5212_CFG_SWTD		0x00000001
#define AR5K_AR5212_CFG_SWTB		0x00000002
#define AR5K_AR5212_CFG_SWRD		0x00000004
#define AR5K_AR5212_CFG_SWRB		0x00000008
#define AR5K_AR5212_CFG_SWRG		0x00000010
#define AR5K_AR5212_CFG_ADHOC		0x00000020
#define AR5K_AR5212_CFG_PHY_OK		0x00000100
#define AR5K_AR5212_CFG_EEBS		0x00000200
#define	AR5K_AR5212_CFG_CLKGD		0x00000400
#define	AR5K_AR5212_CFG_PCI_THRES	0x00060000
#define	AR5K_AR5212_CFG_PCI_THRES_S	17

/*
 * Interrupt enable register
 */
#define AR5K_AR5212_IER		0x0024
#define AR5K_AR5212_IER_DISABLE	0x00000000
#define AR5K_AR5212_IER_ENABLE	0x00000001

/*
 * Transmit configuration register
 */
#define AR5K_AR5212_TXCFG		0x0030
#define AR5K_AR5212_TXCFG_SDMAMR	0x00000007
#define AR5K_AR5212_TXCFG_SDMAMR_S	0
#define AR5K_AR5212_TXCFG_B_MODE	0x00000008
#define AR5K_AR5212_TXCFG_TXFULL	0x000003f0
#define AR5K_AR5212_TXCFG_TXFULL_S	4
#define AR5K_AR5212_TXCFG_TXFULL_0B	0x00000000
#define AR5K_AR5212_TXCFG_TXFULL_64B	0x00000010
#define AR5K_AR5212_TXCFG_TXFULL_128B	0x00000020
#define AR5K_AR5212_TXCFG_TXFULL_192B	0x00000030
#define AR5K_AR5212_TXCFG_TXFULL_256B	0x00000040
#define AR5K_AR5212_TXCFG_TXCONT_ENABLE	0x00000080
#define AR5K_AR5212_TXCFG_DMASIZE	0x00000100
#define AR5K_AR5212_TXCFG_JUMBO_TXE	0x00000400
#define AR5K_AR5212_TXCFG_RTSRND	0x00001000
#define AR5K_AR5212_TXCFG_FRMPAD_DIS	0x00002000
#define AR5K_AR5212_TXCFG_RDY_DIS	0x00004000

/*
 * Receive configuration register
 */
#define AR5K_AR5212_RXCFG			0x0034
#define AR5K_AR5212_RXCFG_SDMAMW		0x00000007
#define AR5K_AR5212_RXCFG_SDMAMW_S		0
#define	AR5K_AR5311_RXCFG_DEFAULT_ANTENNA	0x00000008
#define AR5K_AR5212_RXCFG_ZLFDMA		0x00000010
#define AR5K_AR5212_RXCFG_JUMBO_RXE		0x00000020
#define AR5K_AR5212_RXCFG_JUMBO_WRAP		0x00000040

/*
 * MIB control register
 */
#define AR5K_AR5212_MIBC		0x0040
#define AR5K_AR5212_MIBC_COW		0x00000001
#define AR5K_AR5212_MIBC_FMC		0x00000002
#define AR5K_AR5212_MIBC_CMC		0x00000004
#define AR5K_AR5212_MIBC_MCS		0x00000008

/*
 * Timeout prescale register
 */
#define AR5K_AR5212_TOPS		0x0044
#define	AR5K_AR5212_TOPS_M		0x0000ffff

/*
 * Receive timeout register (no frame received)
 */
#define AR5K_AR5212_RXNOFRM		0x0048
#define	AR5K_AR5212_RXNOFRM_M		0x000003ff

/*
 * Transmit timeout register (no frame sent)
 */
#define AR5K_AR5212_TXNOFRM		0x004c
#define	AR5K_AR5212_TXNOFRM_M		0x000003ff
#define	AR5K_AR5212_TXNOFRM_QCU		0x000ffc00

/*
 * Receive frame gap timeout register
 */
#define AR5K_AR5212_RPGTO		0x0050
#define AR5K_AR5212_RPGTO_M		0x000003ff

/*
 * Receive frame count limit register
 */
#define AR5K_AR5212_RFCNT		0x0054
#define AR5K_AR5212_RFCNT_M		0x0000001f

/*
 * Misc settings register
 */
#define AR5K_AR5212_MISC		0x0058
#define	AR5K_AR5212_MISC_DMA_OBS_M	0x000001e0
#define	AR5K_AR5212_MISC_DMA_OBS_S	5
#define	AR5K_AR5212_MISC_MISC_OBS_M	0x00000e00
#define	AR5K_AR5212_MISC_MISC_OBS_S	9
#define	AR5K_AR5212_MISC_MAC_OBS_LSB_M	0x00007000
#define	AR5K_AR5212_MISC_MAC_OBS_LSB_S	12
#define	AR5K_AR5212_MISC_MAC_OBS_MSB_M	0x00038000
#define	AR5K_AR5212_MISC_MAC_OBS_MSB_S	15

/*
 * Primary interrupt status register
 */
#define AR5K_AR5212_PISR		0x0080
#define AR5K_AR5212_PISR_RXOK		0x00000001
#define AR5K_AR5212_PISR_RXDESC		0x00000002
#define AR5K_AR5212_PISR_RXERR		0x00000004
#define AR5K_AR5212_PISR_RXNOFRM	0x00000008
#define AR5K_AR5212_PISR_RXEOL		0x00000010
#define AR5K_AR5212_PISR_RXORN		0x00000020
#define AR5K_AR5212_PISR_TXOK		0x00000040
#define AR5K_AR5212_PISR_TXDESC		0x00000080
#define AR5K_AR5212_PISR_TXERR		0x00000100
#define AR5K_AR5212_PISR_TXNOFRM	0x00000200
#define AR5K_AR5212_PISR_TXEOL		0x00000400
#define AR5K_AR5212_PISR_TXURN		0x00000800
#define AR5K_AR5212_PISR_MIB		0x00001000
#define AR5K_AR5212_PISR_SWI		0x00002000
#define AR5K_AR5212_PISR_RXPHY		0x00004000
#define AR5K_AR5212_PISR_RXKCM		0x00008000
#define AR5K_AR5212_PISR_SWBA		0x00010000
#define AR5K_AR5212_PISR_BRSSI		0x00020000
#define AR5K_AR5212_PISR_BMISS		0x00040000
#define AR5K_AR5212_PISR_HIUERR		0x00080000
#define AR5K_AR5212_PISR_BNR		0x00100000
#define AR5K_AR5212_PISR_RXCHIRP	0x00200000
#define AR5K_AR5212_PISR_TIM		0x00800000
#define AR5K_AR5212_PISR_BCNMISC	0x00800000
#define AR5K_AR5212_PISR_GPIO		0x01000000
#define AR5K_AR5212_PISR_QCBRORN	0x02000000
#define AR5K_AR5212_PISR_QCBRURN	0x04000000
#define AR5K_AR5212_PISR_QTRIG		0x08000000

/*
 * Secondary interrupt status registers (0 - 4)
 */
#define AR5K_AR5212_SISR0		0x0084
#define AR5K_AR5212_SISR0_QCU_TXOK	0x000003ff
#define AR5K_AR5212_SISR0_QCU_TXDESC	0x03ff0000

#define AR5K_AR5212_SISR1		0x0088
#define AR5K_AR5212_SISR1_QCU_TXERR	0x000003ff
#define AR5K_AR5212_SISR1_QCU_TXEOL	0x03ff0000

#define AR5K_AR5212_SISR2		0x008c
#define AR5K_AR5212_SISR2_QCU_TXURN	0x000003ff
#define	AR5K_AR5212_SISR2_MCABT		0x00100000
#define	AR5K_AR5212_SISR2_SSERR		0x00200000
#define	AR5K_AR5212_SISR2_DPERR		0x00400000
#define	AR5K_AR5212_SISR2_TIM		0x01000000
#define	AR5K_AR5212_SISR2_CAB_END	0x02000000
#define	AR5K_AR5212_SISR2_DTIM_SYNC	0x04000000
#define	AR5K_AR5212_SISR2_BCN_TIMEOUT	0x08000000
#define	AR5K_AR5212_SISR2_CAB_TIMEOUT	0x10000000
#define	AR5K_AR5212_SISR2_DTIM		0x20000000

#define AR5K_AR5212_SISR3		0x0090
#define AR5K_AR5212_SISR3_QCBRORN	0x000003ff
#define AR5K_AR5212_SISR3_QCBRURN	0x03ff0000

#define AR5K_AR5212_SISR4		0x0094
#define AR5K_AR5212_SISR4_QTRIG		0x000003ff

/*
 * Shadow read-and-clear interrupt status registers
 */
#define AR5K_AR5212_RAC_PISR	0x00c0
#define AR5K_AR5212_RAC_SISR0	0x00c4
#define AR5K_AR5212_RAC_SISR1	0x00c8
#define AR5K_AR5212_RAC_SISR2	0x00cc
#define AR5K_AR5212_RAC_SISR3	0c00d0
#define AR5K_AR5212_RAC_SISR4	0c00d4

/*
 * Primary interrupt mask register
 */
#define AR5K_AR5212_PIMR		0x00a0
#define AR5K_AR5212_PIMR_RXOK		0x00000001
#define AR5K_AR5212_PIMR_RXDESC		0x00000002
#define AR5K_AR5212_PIMR_RXERR		0x00000004
#define AR5K_AR5212_PIMR_RXNOFRM	0x00000008
#define AR5K_AR5212_PIMR_RXEOL		0x00000010
#define AR5K_AR5212_PIMR_RXORN		0x00000020
#define AR5K_AR5212_PIMR_TXOK		0x00000040
#define AR5K_AR5212_PIMR_TXDESC		0x00000080
#define AR5K_AR5212_PIMR_TXERR		0x00000100
#define AR5K_AR5212_PIMR_TXNOFRM	0x00000200
#define AR5K_AR5212_PIMR_TXEOL		0x00000400
#define AR5K_AR5212_PIMR_TXURN		0x00000800
#define AR5K_AR5212_PIMR_MIB		0x00001000
#define AR5K_AR5212_PIMR_SWI		0x00002000
#define AR5K_AR5212_PIMR_RXPHY		0x00004000
#define AR5K_AR5212_PIMR_RXKCM		0x00008000
#define AR5K_AR5212_PIMR_SWBA		0x00010000
#define AR5K_AR5212_PIMR_BRSSI		0x00020000
#define AR5K_AR5212_PIMR_BMISS		0x00040000
#define AR5K_AR5212_PIMR_HIUERR		0x00080000
#define AR5K_AR5212_PIMR_BNR		0x00100000
#define AR5K_AR5212_PIMR_RXCHIRP	0x00200000
#define AR5K_AR5212_PIMR_TIM		0x00800000
#define AR5K_AR5212_PIMR_BCNMISC	0x00800000
#define AR5K_AR5212_PIMR_GPIO		0x01000000
#define AR5K_AR5212_PIMR_QCBRORN	0x02000000
#define AR5K_AR5212_PIMR_QCBRURN	0x04000000
#define AR5K_AR5212_PIMR_QTRIG		0x08000000

/*
 * Secondary interrupt mask registers (0 - 4)
 */
#define AR5K_AR5212_SIMR0		0x00a4
#define AR5K_AR5212_SIMR0_QCU_TXOK	0x000003ff
#define AR5K_AR5212_SIMR0_QCU_TXOK_S	0
#define AR5K_AR5212_SIMR0_QCU_TXDESC	0x03ff0000
#define AR5K_AR5212_SIMR0_QCU_TXDESC_S	16

#define AR5K_AR5212_SIMR1		0x00a8
#define AR5K_AR5212_SIMR1_QCU_TXERR	0x000003ff
#define AR5K_AR5212_SIMR1_QCU_TXERR_S	0
#define AR5K_AR5212_SIMR1_QCU_TXEOL	0x03ff0000
#define AR5K_AR5212_SIMR1_QCU_TXEOL_S	16

#define AR5K_AR5212_SIMR2		0x00ac
#define AR5K_AR5212_SIMR2_QCU_TXURN	0x000003ff
#define AR5K_AR5212_SIMR2_QCU_TXURN_S	0
#define	AR5K_AR5212_SIMR2_MCABT		0x00100000
#define	AR5K_AR5212_SIMR2_SSERR		0x00200000
#define	AR5K_AR5212_SIMR2_DPERR		0x00400000
#define	AR5K_AR5212_SIMR2_TIM		0x01000000
#define	AR5K_AR5212_SIMR2_CAB_END	0x02000000
#define	AR5K_AR5212_SIMR2_DTIM_SYNC	0x04000000
#define	AR5K_AR5212_SIMR2_BCN_TIMEOUT	0x08000000
#define	AR5K_AR5212_SIMR2_CAB_TIMEOUT	0x10000000
#define	AR5K_AR5212_SIMR2_DTIM		0x20000000

#define AR5K_AR5212_SIMR3		0x00b0
#define AR5K_AR5212_SIMR3_QCBRORN	0x000003ff
#define AR5K_AR5212_SIMR3_QCBRORN_S	0
#define AR5K_AR5212_SIMR3_QCBRURN	0x03ff0000
#define AR5K_AR5212_SIMR3_QCBRURN_S	16

#define AR5K_AR5212_SIMR4		0x00b4
#define AR5K_AR5212_SIMR4_QTRIG		0x000003ff
#define AR5K_AR5212_SIMR4_QTRIG_S	0

/*
 * Decompression mask registers
 */
#define AR5K_AR5212_DCM_ADDR	0x0400
#define AR5K_AR5212_DCM_DATA	0x0404

/*
 * Decompression configuration registers
 */
#define AR5K_AR5212_DCCFG	0x0420

/*
 * Compression configuration registers
 */
#define AR5K_AR5212_CCFG	0x0600
#define AR5K_AR5212_CCFG_CUP	0x0604

/*
 * Compression performance counter registers
 */
#define AR5K_AR5212_CPC0	0x0610
#define AR5K_AR5212_CPC1	0x0614
#define AR5K_AR5212_CPC2	0x0618
#define AR5K_AR5212_CPC3	0x061c
#define AR5K_AR5212_CPCORN	0x0620

/*
 * Queue control unit (QCU) registers (0 - 9)
 */
#define	AR5K_AR5212_QCU(_n, _a)		(((_n) << 2) + _a)

/*
 * QCU Transmit descriptor pointer registers
 */
#define AR5K_AR5212_QCU_TXDP(_n)	AR5K_AR5212_QCU(_n, 0x0800)

/*
 * QCU Transmit enable register
 */
#define AR5K_AR5212_QCU_TXE		0x0840

/*
 * QCU Transmit disable register
 */
#define AR5K_AR5212_QCU_TXD		0x0880

/*
 * QCU CBR configuration registers
 */
#define	AR5K_AR5212_QCU_CBRCFG(_n)		AR5K_AR5212_QCU(_n, 0x08c0)
#define	AR5K_AR5212_QCU_CBRCFG_INTVAL		0x00ffffff
#define AR5K_AR5212_QCU_CBRCFG_INTVAL_S		0
#define	AR5K_AR5212_QCU_CBRCFG_ORN_THRES	0xff000000
#define AR5K_AR5212_QCU_CBRCFG_ORN_THRES_S	24

/*
 * QCU Ready time configuration registers
 */
#define	AR5K_AR5212_QCU_RDYTIMECFG(_n)		AR5K_AR5212_QCU(_n, 0x0900)
#define	AR5K_AR5212_QCU_RDYTIMECFG_INTVAL	0x00ffffff
#define AR5K_AR5212_QCU_RDYTIMECFG_INTVAL_S	0
#define	AR5K_AR5212_QCU_RDYTIMECFG_DURATION	0x00ffffff
#define	AR5K_AR5212_QCU_RDYTIMECFG_ENABLE	0x01000000

/*
 * QCU one shot arm set registers
 */
#define	AR5K_AR5212_QCU_ONESHOTARMS(_n)	AR5K_AR5212_QCU(_n, 0x0940)
#define	AR5K_AR5212_QCU_ONESHOTARMS_M	0x0000ffff

/*
 * QCU one shot arm clear registers
 */
#define	AR5K_AR5212_QCU_ONESHOTARMC(_n)	AR5K_AR5212_QCU(_n, 0x0980)
#define	AR5K_AR5212_QCU_ONESHOTARMC_M	0x0000ffff

/*
 * QCU misc registers
 */
#define AR5K_AR5212_QCU_MISC(_n)		AR5K_AR5212_QCU(_n, 0x09c0)
#define	AR5K_AR5212_QCU_MISC_FRSHED_M		0x0000000f
#define	AR5K_AR5212_QCU_MISC_FRSHED_ASAP	0
#define	AR5K_AR5212_QCU_MISC_FRSHED_CBR		1
#define	AR5K_AR5212_QCU_MISC_FRSHED_DBA_GT	2
#define	AR5K_AR5212_QCU_MISC_FRSHED_TIM_GT	3
#define	AR5K_AR5212_QCU_MISC_FRSHED_BCN_SENT_GT	4
#define	AR5K_AR5212_QCU_MISC_ONESHOT_ENABLE	0x00000010
#define	AR5K_AR5212_QCU_MISC_CBREXP		0x00000020
#define	AR5K_AR5212_QCU_MISC_CBREXP_BCN		0x00000040
#define	AR5K_AR5212_QCU_MISC_BCN_ENABLE		0x00000080
#define	AR5K_AR5212_QCU_MISC_CBR_THRES_ENABLE	0x00000100
#define	AR5K_AR5212_QCU_MISC_TXE		0x00000200
#define	AR5K_AR5212_QCU_MISC_CBR		0x00000400
#define	AR5K_AR5212_QCU_MISC_DCU_EARLY		0x00000800

/*
 * QCU status registers
 */
#define AR5K_AR5212_QCU_STS(_n)		AR5K_AR5212_QCU(_n, 0x0a00)
#define	AR5K_AR5212_QCU_STS_FRMPENDCNT	0x00000003
#define	AR5K_AR5212_QCU_STS_CBREXPCNT	0x0000ff00

/*
 * QCU ready time shutdown register
 */
#define AR5K_AR5212_QCU_RDYTIMESHDN	0x0a40
#define AR5K_AR5212_QCU_RDYTIMESHDN_M	0x000003ff

/*
 * QCU compression buffer base registers
 */
#define AR5K_AR5212_QCU_CBB_SELECT	0x0b00
#define AR5K_AR5212_QCU_CBB_ADDR	0x0b04

/*
 * QCU compression buffer configuration register
 */
#define AR5K_AR5212_QCU_CBCFG	0x0b08

/*
 * DCF control unit (DCU) registers (0 - 9)