ar5212var.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

/*	$OpenBSD: ar5212var.h,v 1.10 2005/12/18 17:59:58 reyk Exp $	*/

/*
 * Copyright (c) 2004, 2005 Reyk Floeter <[e-mail]>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * Specific definitions for the Atheros AR5001 Wireless LAN chipset
 * (AR5212/AR5311).
 */

#ifndef _AR5K_AR5212_VAR_H
#define _AR5K_AR5212_VAR_H

#include "ar5xxx.h"

/*
 * Define a "magic" code for the AR5212 (the HAL layer wants it)
 */

#define AR5K_AR5212_MAGIC		0x0000145c /* 5212 */
#define AR5K_AR5212_TX_NUM_QUEUES	10

#if BYTE_ORDER == BIG_ENDIAN
#define AR5K_AR5212_INIT_CFG	(					\
	AR5K_AR5212_CFG_SWTD | AR5K_AR5212_CFG_SWRD			\
)
#else
#define AR5K_AR5212_INIT_CFG	0x00000000
#endif

/*
 * Internal RX/TX descriptor structures
 * (rX: reserved fields possibily used by future versions of the ar5k chipset)
 */

struct ar5k_ar5212_rx_desc {
	/*
	 * RX control word 0
	 */
	u_int32_t	rx_control_0;

#define AR5K_AR5212_DESC_RX_CTL0			0x00000000

	/*
	 * RX control word 1
	 */
	u_int32_t	rx_control_1;

#define AR5K_AR5212_DESC_RX_CTL1_BUF_LEN		0x00000fff
#define AR5K_AR5212_DESC_RX_CTL1_INTREQ			0x00002000
} __packed;

struct ar5k_ar5212_rx_status {
	/*
	 * RX status word 0
	 */
	u_int32_t	rx_status_0;

#define AR5K_AR5212_DESC_RX_STATUS0_DATA_LEN		0x00000fff
#define AR5K_AR5212_DESC_RX_STATUS0_MORE		0x00001000
#define AR5K_AR5212_DESC_RX_STATUS0_DECOMP_CRC_ERROR	0x00002000
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE	0x000f8000
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_RATE_S	15
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL	0x0ff00000
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_SIGNAL_S	20
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA	0xf0000000
#define AR5K_AR5212_DESC_RX_STATUS0_RECEIVE_ANTENNA_S	28

	/*
	 * RX status word 1
	 */
	u_int32_t	rx_status_1;

#define AR5K_AR5212_DESC_RX_STATUS1_DONE		0x00000001
#define AR5K_AR5212_DESC_RX_STATUS1_FRAME_RECEIVE_OK	0x00000002
#define AR5K_AR5212_DESC_RX_STATUS1_CRC_ERROR		0x00000004
#define AR5K_AR5212_DESC_RX_STATUS1_DECRYPT_CRC_ERROR	0x00000008
#define AR5K_AR5212_DESC_RX_STATUS1_PHY_ERROR		0x00000010
#define AR5K_AR5212_DESC_RX_STATUS1_MIC_ERROR		0x00000020
#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_VALID	0x00000100
#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX		0x0000fe00
#define AR5K_AR5212_DESC_RX_STATUS1_KEY_INDEX_S		9
#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP	0x7fff0000
#define AR5K_AR5212_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S	16
#define AR5K_AR5212_DESC_RX_STATUS1_KEY_CACHE_MISS	0x80000000
} __packed;

struct ar5k_ar5212_rx_error {
	/*
	 * RX error word 0
	 */
	u_int32_t	rx_error_0;

#define AR5K_AR5212_DESC_RX_ERROR0			0x00000000

	/*
	 * RX error word 1
	 */
	u_int32_t	rx_error_1;

#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE	0x0000ff00
#define AR5K_AR5212_DESC_RX_ERROR1_PHY_ERROR_CODE_S	8
} __packed;

#define AR5K_AR5212_DESC_RX_PHY_ERROR_NONE		0x00
#define AR5K_AR5212_DESC_RX_PHY_ERROR_TIMING		0x20
#define AR5K_AR5212_DESC_RX_PHY_ERROR_PARITY		0x40
#define AR5K_AR5212_DESC_RX_PHY_ERROR_RATE		0x60
#define AR5K_AR5212_DESC_RX_PHY_ERROR_LENGTH		0x80
#define AR5K_AR5212_DESC_RX_PHY_ERROR_64QAM		0xa0
#define AR5K_AR5212_DESC_RX_PHY_ERROR_SERVICE		0xc0
#define AR5K_AR5212_DESC_RX_PHY_ERROR_TRANSMITOVR	0xe0

struct ar5k_ar5212_tx_desc {
	/*
	 * TX control word 0
	 */
	u_int32_t	tx_control_0;

#define AR5K_AR5212_DESC_TX_CTL0_FRAME_LEN		0x00000fff
#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER		0x003f0000
#define AR5K_AR5212_DESC_TX_CTL0_XMIT_POWER_S		16
#define AR5K_AR5212_DESC_TX_CTL0_RTSENA			0x00400000
#define AR5K_AR5212_DESC_TX_CTL0_VEOL			0x00800000
#define AR5K_AR5212_DESC_TX_CTL0_CLRDMASK		0x01000000
#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT		0x1e000000
#define AR5K_AR5212_DESC_TX_CTL0_ANT_MODE_XMIT_S	25
#define AR5K_AR5212_DESC_TX_CTL0_INTREQ			0x20000000
#define AR5K_AR5212_DESC_TX_CTL0_ENCRYPT_KEY_VALID	0x40000000
#define AR5K_AR5212_DESC_TX_CTL0_CTSENA			0x80000000

	/*
	 * TX control word 1
	 */
	u_int32_t	tx_control_1;

#define AR5K_AR5212_DESC_TX_CTL1_BUF_LEN		0x00000fff
#define AR5K_AR5212_DESC_TX_CTL1_MORE			0x00001000
#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX	0x000fe000
#define AR5K_AR5212_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S	13
#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE		0x00f00000
#define AR5K_AR5212_DESC_TX_CTL1_FRAME_TYPE_S		20
#define AR5K_AR5212_DESC_TX_CTL1_NOACK			0x01000000
#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC		0x06000000
#define AR5K_AR5212_DESC_TX_CTL1_COMP_PROC_S		25
#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN		0x18000000
#define AR5K_AR5212_DESC_TX_CTL1_COMP_IV_LEN_S		27
#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN		0x60000000
#define AR5K_AR5212_DESC_TX_CTL1_COMP_ICV_LEN_S		29

	/*
	 * TX control word 2
	 */
	u_int32_t	tx_control_2;

#define AR5K_AR5212_DESC_TX_CTL2_RTS_DURATION		0x00007fff
#define AR5K_AR5212_DESC_TX_CTL2_DURATION_UPDATE_ENABLE	0x00008000
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0		0x000f0000
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES0_S		16
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1		0x00f00000
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES1_S		20
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2		0x0f000000
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES2_S		24
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3		0xf0000000
#define AR5K_AR5212_DESC_TX_CTL2_XMIT_TRIES3_S		28

	/*
	 * TX control word 3
	 */
	u_int32_t	tx_control_3;

#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE0		0x0000001f
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1		0x000003e0
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE1_S		5
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2		0x00007c00
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE2_S		10
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3		0x000f8000
#define AR5K_AR5212_DESC_TX_CTL3_XMIT_RATE3_S		15
#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE		0x01f00000
#define AR5K_AR5212_DESC_TX_CTL3_RTS_CTS_RATE_S		20
} __packed;

struct ar5k_ar5212_tx_status {
	/*
	 * TX status word 0
	 */
	u_int32_t	tx_status_0;

#define AR5K_AR5212_DESC_TX_STATUS0_FRAME_XMIT_OK	0x00000001
#define AR5K_AR5212_DESC_TX_STATUS0_EXCESSIVE_RETRIES	0x00000002
#define AR5K_AR5212_DESC_TX_STATUS0_FIFO_UNDERRUN	0x00000004
#define AR5K_AR5212_DESC_TX_STATUS0_FILTERED		0x00000008
#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT	0x000000f0
#define AR5K_AR5212_DESC_TX_STATUS0_RTS_FAIL_COUNT_S	4
#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT	0x00000f00
#define AR5K_AR5212_DESC_TX_STATUS0_DATA_FAIL_COUNT_S	8
#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT	0x0000f000
#define AR5K_AR5212_DESC_TX_STATUS0_VIRT_COLL_COUNT_S	12
#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP	0xffff0000
#define AR5K_AR5212_DESC_TX_STATUS0_SEND_TIMESTAMP_S	16

	/*
	 * TX status word 1
	 */
	u_int32_t	tx_status_1;

#define AR5K_AR5212_DESC_TX_STATUS1_DONE		0x00000001
#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM		0x00001ffe
#define AR5K_AR5212_DESC_TX_STATUS1_SEQ_NUM_S		1
#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH	0x001fe000
#define AR5K_AR5212_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S	13
#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX	0x00600000
#define AR5K_AR5212_DESC_TX_STATUS1_FINAL_TS_INDEX_S	21
#define AR5K_AR5212_DESC_TX_STATUS1_COMP_SUCCESS	0x00800000
#define AR5K_AR5212_DESC_TX_STATUS1_XMIT_ANTENNA	0x01000000
} __packed;

/*
 * Public function prototypes
 */
extern ar5k_attach_t ar5k_ar5212_attach;

/*
 * Initial register values which have to be loaded into the
 * card at boot time and after each reset.
 */

struct ar5k_ar5212_ini {
	u_int8_t	ini_flags;
	u_int16_t	ini_register;
	u_int32_t	ini_value;

#define AR5K_INI_FLAG_511X	0x00
#define	AR5K_INI_FLAG_5111	0x01
#define AR5K_INI_FLAG_5112	0x02
#define AR5K_INI_FLAG_BOTH	(AR5K_INI_FLAG_5111 | AR5K_INI_FLAG_5112)
};

#define AR5K_AR5212_INI {						\
	{ AR5K_INI_FLAG_BOTH, 0x000c, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0034, 0x00000005 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0040, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0044, 0x00000008 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0048, 0x00000008 },			\
	{ AR5K_INI_FLAG_BOTH, 0x004c, 0x00000010 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0050, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0054, 0x0000001f },			\
	{ AR5K_INI_FLAG_BOTH, 0x0800, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0804, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0808, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x080c, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0810, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0814, 0x00000000 },			\
	{ AR5K_INI_FLAG_BOTH, 0x0818, 0x00000000 },			\