ar5xxx.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

#define AR5K_HAL_FUNCTION(_hal, _n, _f)	(_hal)->ah_##_f = ar5k_##_n##_##_f
#define AR5K_HAL_FUNCTIONS(_t, _n, _a) \
	_t const HAL_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, \
	    u_int mode); \
	_t void (_a _n##_detach)(struct ath_hal *); \
	/* Reset functions */ \
	_t HAL_BOOL (_a _n##_reset)(struct ath_hal *, HAL_OPMODE, \
	    HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status); \
	_t void (_a _n##_set_opmode)(struct ath_hal *); \
	_t HAL_BOOL (_a _n##_calibrate)(struct ath_hal*, \
	    HAL_CHANNEL *); \
	/* Transmit functions */ \
	_t HAL_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, \
	    HAL_BOOL level); \
	_t int (_a _n##_setup_tx_queue)(struct ath_hal *, HAL_TX_QUEUE, \
	    const HAL_TXQ_INFO *); \
	_t HAL_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \
	    const HAL_TXQ_INFO *); \
	_t HAL_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \
	_t HAL_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \
	_t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \
	_t HAL_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, \
	    u_int32_t phys_addr); \
	_t HAL_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \
	_t HAL_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \
	_t HAL_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, \
	    struct ath_desc *, \
	    u_int packet_length, u_int header_length, HAL_PKT_TYPE type, \
	    u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \
	    u_int antenna_mode, u_int flags, u_int rtscts_rate, \
	    u_int rtscts_duration); \
	_t HAL_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, \
	    struct ath_desc *, \
	    u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, \
	    u_int tx_rate3, u_int tx_tries3); \
	_t HAL_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, \
	    struct ath_desc *, \
	    u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg, const struct ath_desc *); \
	_t HAL_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, \
	    struct ath_desc *); \
	_t HAL_BOOL (_a _n##_has_veol)(struct ath_hal *); \
	/* Receive Functions */ \
	_t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \
	_t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \
	_t void (_a _n##_start_rx)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \
	_t void (_a _n##_start_rx_pcu)(struct ath_hal*); \
	_t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \
	_t void (_a _n##_set_mcast_filter)(struct ath_hal*, \
	    u_int32_t filter0, u_int32_t filter1); \
	_t HAL_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, \
	    u_int32_t index); \
	_t HAL_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, \
	    u_int32_t index); \
	_t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \
	_t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \
	_t HAL_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, \
	    struct ath_desc *, u_int32_t size, u_int flags); \
	_t HAL_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, \
	    struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next); \
	_t void (_a _n##_set_rx_signal)(struct ath_hal *, const HAL_NODE_STATS *); \
	/* Misc Functions */ \
	_t void (_a _n##_dump_state)(struct ath_hal *); \
	_t HAL_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int request,\
				     const void *args, u_int32_t argsize,\
				     void **result, u_int32_t *resultsize);\
	_t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \
	_t HAL_BOOL (_a _n##_set_lladdr)(struct ath_hal *, \
	    const u_int8_t*); \
	_t HAL_BOOL (_a _n##_set_regdomain)(struct ath_hal*, \
	    u_int16_t, HAL_STATUS *); \
	_t void (_a _n##_set_ledstate)(struct ath_hal*, HAL_LED_STATE); \
	_t void (_a _n##_set_associd)(struct ath_hal*, \
	    const u_int8_t *bssid, u_int16_t assocId); \
	_t HAL_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, \
	    u_int32_t gpio); \
	_t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \
	    u_int32_t gpio); \
	_t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \
	_t HAL_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, \
	    u_int32_t val); \
	_t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \
	_t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \
	_t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \
	_t void (_a _n##_reset_tsf)(struct ath_hal*); \
	_t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \
	_t void (_a _n##_update_mib_counters)(struct ath_hal*, \
	    HAL_MIB_STATS*); \
	_t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \
	    HAL_CIPHER); \
	_t HAL_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int);	\
	_t u_int (_a _n##_get_slot_time)(struct ath_hal*);		\
	_t HAL_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \
	_t u_int (_a _n##_get_ack_timeout)(struct ath_hal*);		\
	_t HAL_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int);	\
	_t u_int (_a _n##_get_cts_timeout)(struct ath_hal*);		\
	/* Key Cache Functions */ \
	_t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_reset_key)(struct ath_hal*, \
	    u_int16_t); \
	_t HAL_BOOL (_a _n##_is_key_valid)(struct ath_hal *, \
	    u_int16_t); \
	_t HAL_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, \
	    const HAL_KEYVAL *, const u_int8_t *, int);	\
	_t HAL_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, \
	    u_int16_t, const u_int8_t *); \
	/* Power Management Functions */ \
	_t HAL_BOOL (_a _n##_set_power)(struct ath_hal*, \
	    HAL_POWER_MODE mode, \
	    HAL_BOOL set_chip, u_int16_t sleep_duration); \
	_t HAL_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \
	_t HAL_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, \
	    u_int16_t); \
	_t HAL_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \
	/* Beacon Management Functions */ \
	_t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, \
	    u_int32_t intval); \
	_t void (_a _n##_set_beacon_timers)(struct ath_hal *, \
	    const HAL_BEACON_STATE *); \
	_t void (_a _n##_reset_beacon)(struct ath_hal *); \
	_t HAL_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, \
	    HAL_BUS_ADDR); \
	/* Interrupt functions */ \
	_t HAL_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \
	_t HAL_BOOL (_a _n##_get_isr)(struct ath_hal *, \
	    u_int32_t *); \
	_t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \
	_t HAL_INT (_a _n##_set_intr)(struct ath_hal *, HAL_INT); \
	/* Chipset functions (ar5k-specific, non-HAL) */ \
	_t HAL_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \
	_t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \
	_t HAL_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \
	_t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, \
	    u_int16_t *data); \
	_t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, \
	    u_int16_t data); \
	/* Functions not found in OpenBSD */ \
	_t HAL_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, HAL_TXQ_INFO *);\
	_t HAL_STATUS (_a _n##_get_capability)(struct ath_hal *, HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t *); \
	_t u_int32_t  (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \
	_t HAL_BOOL (_a _n##_phy_disable)(struct ath_hal *);\
	_t void (_a _n##_set_pcu_config)(struct ath_hal *);\
	/*Totaly unimplemented*/ \
	_t HAL_BOOL (_a _n##_set_capability)(struct ath_hal *, HAL_CAPABILITY_TYPE, u_int32_t, u_int32_t, HAL_STATUS *) ; \
	_t void (_a _n##_proc_mib_event)(struct ath_hal *, const HAL_NODE_STATS *) ; \
	_t void (_a _n##_get_tx_inter_queue)(struct ath_hal *, u_int32_t *); \
	_t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int32_t); \
	_t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int);\
	_t u_int  (_a _n ##_get_def_antenna)(struct ath_hal *);

#define AR5K_MAX_GPIO		10
#define AR5K_MAX_RF_BANKS	8

struct ath_hal {
	u_int32_t		ah_magic;
	u_int32_t		ah_abi;
	u_int16_t		ah_device;
	u_int16_t		ah_sub_vendor;

	HAL_SOFTC		ah_sc;
	bus_space_tag_t		ah_st;
	bus_space_handle_t 	ah_sh;
	HAL_CTRY_CODE	ah_country_code;

	HAL_INT			ah_imr;

	HAL_OPMODE		ah_op_mode;
	HAL_POWER_MODE		ah_power_mode;
	HAL_CHANNEL		ah_current_channel;
	HAL_BOOL		ah_turbo;
	HAL_BOOL		ah_calibration;
	HAL_BOOL		ah_running;
	HAL_RFGAIN		ah_rf_gain;

	HAL_RATE_TABLE		ah_rt_11a;
	HAL_RATE_TABLE		ah_rt_11b;
	HAL_RATE_TABLE		ah_rt_11g;
	HAL_RATE_TABLE		ah_rt_turbo;
	HAL_RATE_TABLE		ah_rt_xr;

	u_int32_t		ah_mac_srev;
	u_int16_t		ah_mac_version;
	u_int16_t		ah_mac_revision;
	u_int16_t		ah_phy_revision;
	u_int16_t		ah_radio_5ghz_revision;
	u_int16_t		ah_radio_2ghz_revision;

	enum ar5k_version	ah_version;
	enum ar5k_radio		ah_radio;
	u_int32_t		ah_phy;

	HAL_BOOL		ah_5ghz;
	HAL_BOOL		ah_2ghz;

#define ah_regdomain		ah_capabilities.cap_regdomain.reg_current
#define ah_regdomain_hw		ah_capabilities.cap_regdomain.reg_hw
#define ah_modes		ah_capabilities.cap_mode
#define ah_ee_version		ah_capabilities.cap_eeprom.ee_version
#define ah_countryCode		ah_country_code
#define ah_macVersion		ah_mac_version
#define ah_macRev		ah_mac_revision
#define ah_phyRev		ah_phy_revision
#define ah_analog5GhzRev	ah_radio_5ghz_revision
#define ah_analog2GhzRev	ah_radio_2ghz_revision

	u_int32_t		ah_atim_window;
	u_int32_t		ah_aifs;
	u_int32_t		ah_cw_min;
	u_int32_t		ah_cw_max;
	HAL_BOOL		ah_software_retry;
	u_int32_t		ah_limit_tx_retries;

	u_int32_t		ah_antenna[AR5K_EEPROM_N_MODES][HAL_ANT_MAX];
	HAL_BOOL		ah_ant_diversity;

	u_int8_t		ah_sta_id[IEEE80211_ADDR_LEN];
	u_int8_t		ah_bssid[IEEE80211_ADDR_LEN];

	u_int32_t		ah_gpio[AR5K_MAX_GPIO];
	int			ah_gpio_npins;

	ar5k_capabilities_t	ah_capabilities;

	HAL_TXQ_INFO		ah_txq[HAL_NUM_TX_QUEUES];
	u_int32_t		ah_txq_interrupts;

	u_int32_t		*ah_rf_banks;
	size_t			ah_rf_banks_size;
	struct ar5k_gain	ah_gain;
	u_int32_t		ah_offset[AR5K_MAX_RF_BANKS];

	struct {
		u_int16_t	txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
		u_int16_t	txp_rates[AR5K_MAX_RATES];
		int16_t		txp_min, txp_max;
		HAL_BOOL	txp_tpc;
		int16_t		txp_ofdm;
	} ah_txpower;

	struct {
		HAL_BOOL	r_enabled;
		int		r_last_alert;
		HAL_CHANNEL	r_last_channel;
	} ah_radar;

	/*
	 * Function pointers
	 */
	AR5K_HAL_FUNCTIONS(, ah, *);

};

/*
 * Common silicon revision/version values
 */
enum ar5k_srev_type {
	AR5K_VERSION_VER,
	AR5K_VERSION_REV,
	AR5K_VERSION_RAD
};

struct ar5k_srev_name {
	const char		*sr_name;
	enum ar5k_srev_type	sr_type;
	u_int			sr_val;
};

#define AR5K_SREV_NAME	{						\
	{ "5210",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5210 },	\
	{ "5311",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5311 },	\
	{ "5311a",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5311A },\
	{ "5311b",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5311B },\
	{ "5211",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5211 },	\
	{ "5212",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5212 },	\
	{ "5213",	AR5K_VERSION_VER,	AR5K_SREV_VER_AR5213 },	\
	{ "xxxx",	AR5K_VERSION_VER,	AR5K_SREV_UNKNOWN },	\
	{ "5110",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5110 },	\
	{ "5111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111 },	\
	{ "2111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2111 },	\
	{ "5112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112 },	\
	{ "5112a",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112A },	\ 
	{ "2112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112 },	\
	{ "2112a",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112A },	\
	{ "xxxx",	AR5K_VERSION_RAD,	AR5K_SREV_UNKNOWN }	\
}

#define AR5K_SREV_UNKNOWN		0xffff

#define AR5K_SREV_VER_AR5210	0x00
#define AR5K_SREV_VER_AR5311	0x10
#define AR5K_SREV_VER_AR5311A	0x20
#define AR5K_SREV_VER_AR5311B	0x30
#define AR5K_SREV_VER_AR5211	0x40
#define AR5K_SREV_VER_AR5212	0x50
#define AR5K_SREV_VER_AR5213	0x55
#define AR5K_SREV_VER_UNSUPP	0x60

#define AR5K_SREV_RAD_5110	0x00
#define AR5K_SREV_RAD_5111	0x10
#define AR5K_SREV_RAD_5111A	0x15
#define AR5K_SREV_RAD_2111	0x20
#define AR5K_SREV_RAD_5112	0x30
#define AR5K_SREV_RAD_5112A	0x35
#define AR5K_SREV_RAD_2112	0x40
#define AR5K_SREV_RAD_2112A	0x45
#define AR5K_SREV_RAD_UNSUPP	0x50

/*
 * Misc defines
 */

#define HAL_ABI_VERSION		0x04090901 /* YYMMDDnn */

#define AR5K_ELEMENTS(_array)	(sizeof(_array) / sizeof(_array[0]))

typedef struct ath_hal * (ar5k_attach_t)
	(u_int16_t, HAL_SOFTC, HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS *);

typedef HAL_BOOL (ar5k_rfgain_t)
	(struct ath_hal *, HAL_CHANNEL *, u_int);

/*
 * Some tuneable values (these should be changeable by the user)
 */

#define AR5K_TUNE_DMA_BEACON_RESP		2
#define AR5K_TUNE_SW_BEACON_RESP		10
#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF	0
#define AR5K_TUNE_RADAR_ALERT			AH_FALSE
#define AR5K_TUNE_MIN_TX_FIFO_THRES		1
#define AR5K_TUNE_MAX_TX_FIFO_THRES		((IEEE80211_MAX_LEN / 64) + 1)
#define AR5K_TUNE_RSSI_THRES			1792
#define AR5K_TUNE_REGISTER_TIMEOUT		20000
#define AR5K_TUNE_REGISTER_DWELL_TIME		20000
#define AR5K_TUNE_BEACON_INTERVAL		100
#define AR5K_TUNE_AIFS				2
#define AR5K_TUNE_AIFS_11B			2
#define AR5K_TUNE_AIFS_XR			0
#define AR5K_TUNE_CWMIN				15
#define AR5K_TUNE_CWMIN_11B			31
#define AR5K_TUNE_CWMIN_XR			3
#define AR5K_TUNE_CWMAX				1023
#define AR5K_TUNE_CWMAX_11B			1023
#define AR5K_TUNE_CWMAX_XR			7
#define AR5K_TUNE_NOISE_FLOOR			-72
#define AR5K_TUNE_MAX_TXPOWER			60
#define AR5K_TUNE_DEFAULT_TXPOWER		30
#define AR5K_TUNE_TPC_TXPOWER			AH_TRUE
#define AR5K_TUNE_ANT_DIVERSITY			AH_TRUE
#define AR5K_TUNE_HWTXTRIES			4

/* Default regulation domain if stored value EEPROM value is invalid */
#define AR5K_TUNE_REGDOMAIN	DMN_FCC2_FCCA	/* Canada */
#define AR5K_TUNE_CTRY		CTRY_DEFAULT

/* token to use for aifs, cwmin, cwmax in MadWiFi */
#define	HAL_TXQ_USEDEFAULT	((u_int32_t) -1)

/*
 * Common initial register values
 */

#define AR5K_INIT_MODE				(			\
	IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN			\
)
#define AR5K_INIT_TX_LATENCY			502
#define AR5K_INIT_USEC				39
#define AR5K_INIT_USEC_TURBO			79
#define AR5K_INIT_USEC_32			31
#define AR5K_INIT_CARR_SENSE_EN			1
#define AR5K_INIT_PROG_IFS			920
#define AR5K_INIT_PROG_IFS_TURBO		960
#define AR5K_INIT_EIFS				3440
#define AR5K_INIT_EIFS_TURBO			6880
#define AR5K_INIT_SLOT_TIME			396
#define AR5K_INIT_SLOT_TIME_TURBO		480
#define AR5K_INIT_ACK_CTS_TIMEOUT		1024