ar5xxx.h

无线网卡驱动 固件程序 There are currently 3 "programming generations" of Atheros 802.11 wireless devices (

/*	$OpenBSD: ar5xxx.h,v 1.30 2005/12/18 17:59:58 reyk Exp $	*/

/*
 * Copyright (c) 2004, 2005 Reyk Floeter <[e-mail]>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * HAL interface for Atheros Wireless LAN devices.
 *
 * ar5k is a free replacement of the binary-only HAL used by some drivers
 * for Atheros chipsets. While using a different ABI, it tries to be
 * source-compatible with the original (non-free) HAL interface.
 *
 * Many thanks to various contributors who supported the development of
 * ar5k with hard work and useful information. And, of course, for all the
 * people who encouraged me to continue this work which has been based
 * on my initial approach found on http://team.vantronix.net/ar5k/.
 */

#ifndef _AR5K_H
#define _AR5K_H

/*Os dependent definitions*/
#include "ah_osdep.h"

/*Regulatory domain & Channel definitions*/
#include "ieee80211_regdomain.h"

/*Options*/
#include "opt_ah.h"

/*
 *Translation for MadWiFi combatibility
 *(damn this is changed AGAIN in if_ath.pci :P)
 */
#include "translation.h"

/*net80211 definitions needed for channels etc*/
#include "../net80211/ieee80211.h"
#include "../net80211/if_media.h"
#include "../net80211/ieee80211_var.h"
#include "../net80211/ieee80211_linux.h"
#include "../net80211/ieee80211_radiotap.h"

#define IEEE80211_ADDR_LEN      6       /* size of 802.11 address */
#define ETHER_ADDR_LEN          6       /* length of an Ethernet address */
static const u_char etherbroadcastaddr[ETHER_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; /*http://fxr.watson.org/fxr/ident?i=etherbroadcastaddr*/
//#define etherbroadcastaddr 0xff

typedef struct {
	u_int32_t	ns_avgbrssi;	/* average beacon rssi */
	u_int32_t	ns_avgrssi;	/* average data rssi */
	u_int32_t	ns_avgtxrssi;	/* average tx rssi */
} HAL_NODE_STATS;

/* eXtendent Range (?) stuff */
#define IEEE80211_T_XR 7
#define IEEE80211_CHAN_XR		0x1000  /* XXX */
#define	IEEE80211_IS_CHAN_XR(_c) \
	(((_c)->ic_flags & IEEE80211_CHAN_XR) != 0)

/*
 * Possible chipsets (could appear in different combinations)
 */

enum ar5k_version {
	AR5K_AR5210	= 0,
	AR5K_AR5211	= 1,
	AR5K_AR5212	= 2,
};

enum ar5k_radio {
	AR5K_AR5110	= 0,
	AR5K_AR5111	= 1,
	AR5K_AR5112	= 2,
};

/*
 * Generic definitions
 */

/*
 * Status codes that may be returned by the HAL.  Note that
 * interfaces that return a status code set it only when an
 * error occurs--i.e. you cannot check it for success.
 */
typedef enum {
	HAL_OK			= 0,		/* No error */
	HAL_ENXIO		= 1,		/* No hardware present */
	HAL_ENOMEM		= 2,		/* Memory allocation failed */
	HAL_EIO			= 3,		/* Hardware didn't respond as expected */
	HAL_EEMAGIC		= 4,		/* EEPROM magic number invalid */
	HAL_EEVERSION		= 5,		/* EEPROM version invalid */
	HAL_EELOCKED		= 6,		/* EEPROM unreadable */
	HAL_EEBADSUM		= 7,		/* EEPROM checksum invalid */
	HAL_EEREAD		= 8,		/* EEPROM read problem */
	HAL_EEBADMAC		= 9,		/* EEPROM mac address invalid */
	HAL_EESIZE		= 10,	/* EEPROM size not supported */
	HAL_EEWRITE		= 11,	/* Attempt to change write-locked EEPROM */
	HAL_EINVAL		= 12,	/* Invalid parameter to function */
	HAL_ENOTSUPP		= 13,	/* Hardware revision not supported */
	HAL_ESELFTEST		= 14,	/* Hardware self-test failed */
	HAL_EINPROGRESS		= 15,	/* Operation incomplete */
} HAL_STATUS;

typedef enum {
	AH_FALSE = 0,	/* NB: lots of code assumes false is zero */
	AH_TRUE,
} HAL_BOOL;

enum {
	HAL_MODE_11A			= 0x001,		/* 11a channels */
	HAL_MODE_TURBO			= 0x002,		/* 11a turbo-only channels */
	HAL_MODE_11B			= 0x004,		/* 11b channels */
	HAL_MODE_PUREG			= 0x008,		/* 11g channels (OFDM only) */
	HAL_MODE_11G			= 0x010,		/* 11g channels (OFDM/CCK) */
//	HAL_MODE_11G			= 0x008,		/* XXX historical */
	HAL_MODE_108G			= 0x020,		/* 11g+Turbo channels */
	HAL_MODE_108A			= 0x040,		/* 11a+Turbo channels */
	HAL_MODE_XR			= 0x100,		/* XR channels */
	HAL_MODE_11A_HALF_RATE 		= 0x200,		/* 11A half rate channels */
	HAL_MODE_11A_QUARTER_RATE 	= 0x400,		/* 11A quarter rate channels */
	HAL_MODE_ALL			= 0xfff
};


typedef enum {
	HAL_M_STA	 = 1,
	HAL_M_IBSS 	 = 0,
	HAL_M_HOSTAP  = 6,
	HAL_M_MONITOR = 8,
} HAL_OPMODE;


/*
 * TX queues
 */

/*
 * Transmit queue types/numbers.  These are used to tag
 * each transmit queue in the hardware and to identify a set
 * of transmit queues for operations such as start/stop dma.
 */
typedef enum {
	HAL_TX_QUEUE_INACTIVE = 0,	/* queue is inactive/unused */
	HAL_TX_QUEUE_DATA,		/* data xmit q's */
	HAL_TX_QUEUE_BEACON,		/* beacon xmit q */
	HAL_TX_QUEUE_CAB,		/* "crap after beacon" xmit q */
	HAL_TX_QUEUE_PSPOLL,		/* u-apsd power save xmit q (I guess) */
} HAL_TX_QUEUE;

#define	HAL_NUM_TX_QUEUES	10		/* max possible # of queues */

typedef enum {
	HAL_TX_QUEUE_ID_DATA_MIN 	= 0,
	HAL_TX_QUEUE_ID_DATA_MAX 	= 6,
	HAL_TX_QUEUE_ID_PSPOLL 	= 7,
	HAL_TX_QUEUE_ID_BEACON 	= 8,
	HAL_TX_QUEUE_ID_CAB 		= 9,
} HAL_TX_QUEUE_ID;

/*
 * Transmit queue subtype.  These map directly to
 * WME Access Categories (except for UPSD).  Refer
 * to Table 5 of the WME spec.
 */
typedef enum {
	HAL_WME_AC_BK	= 0,			/* background access category */
	HAL_WME_AC_BE	= 1, 			/* best effort access category*/
	HAL_WME_AC_VI	= 2,			/* video access category */
	HAL_WME_AC_VO	= 3,			/* voice access category */
	HAL_WME_UPSD	= 4,			/* uplink power save */
	HAL_XR_DATA	= 5,			/* uplink power save */
} HAL_TX_QUEUE_SUBTYPE;

/*
 * Transmit queue flags that control various
 * operational parameters.
 */

#define AR5K_TXQ_FLAG_TXINT_ENABLE			0x0001	/* enable TXOK interrupt */
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE			0x0002	/* enable TXDESC interrupt */
#define AR5K_TXQ_FLAG_BACKOFF_DISABLE			0x0004	/* disable Post Backoff  */
#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE		0x0008	/* compression enabled */
#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE		0x0010	/* enable ready time expiry policy */
#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE		0x0020	/* enable backoff while sending fragment burst*/
#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS			0x0040	/* disable backoff while sending fragment burst */
#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE			0x0080	/* enable TXEOL interrupt */

typedef enum {
	TXQ_FLAG_TXOKINT_ENABLE	    = AR5K_TXQ_FLAG_TXINT_ENABLE,    	/* enable TXOK interrupt */
	TXQ_FLAG_TXERRINT_ENABLE    = AR5K_TXQ_FLAG_TXINT_ENABLE,    	/* enable TXERR interrupt */
	TXQ_FLAG_TXDESCINT_ENABLE   = AR5K_TXQ_FLAG_TXDESCINT_ENABLE,   /* enable TXDESC interrupt */
	TXQ_FLAG_TXEOLINT_ENABLE    = AR5K_TXQ_FLAG_TXEOLINT_ENABLE,    /* enable TXEOL interrupt */
//	TXQ_FLAG_TXURNINT_ENABLE    = 0x0008,    			/* enable TXURN interrupt */
	TXQ_FLAG_BACKOFF_DISABLE    = AR5K_TXQ_FLAG_BACKOFF_DISABLE,    /* disable Post Backoff  */
	TXQ_FLAG_COMPRESSION_ENABLE = AR5K_TXQ_FLAG_COMPRESSION_ENABLE, /* compression enabled */
	TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, /* enable ready time expiry policy */
	TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, /* enable backoff while sending fragment burst*/
} HAL_TX_QUEUE_FLAGS;

typedef struct {
	u_int32_t			tqi_ver;	/* hal TXQ version */
	HAL_TX_QUEUE			tqi_type;	
	HAL_TX_QUEUE_SUBTYPE		tqi_subtype;	/* subtype if applicable */
	u_int16_t			tqi_flags;	/* flags (see above) */
	u_int32_t			tqi_priority;	
	u_int32_t			tqi_aifs;	/*Arbitrated Interframe Space*/
	int32_t				tqi_cw_min;	/*Minimum Contention Window*/
	int32_t				tqi_cw_max;	/*Maximum Contention Window*/
	u_int32_t			tqi_cbr_period;
	u_int32_t			tqi_cbr_overflow_limit;
	u_int32_t			tqi_burst_time;
	u_int32_t			tqi_ready_time;

//	u_int16_t			tqi_shretry;	/* rts retry limit */
//	u_int16_t			tqi_lgretry;	/* long retry limit (not used)*/
//	u_int32_t			tqi_compBuf; 	/* compression buffer phys addr */

#define tqi_cwmin			tqi_cw_min
#define tqi_cwmax			tqi_cw_max
#define tqi_cbrPeriod			tqi_cbr_period
#define tqi_cbrOverflowLimit		tqi_cbr_overflow_limit
#define tqi_burstTime			tqi_burst_time
#define tqi_readyTime			tqi_ready_time
#define tqi_qflags			tqi_flags

} HAL_TXQ_INFO;

/*
 * Transmit packet types.
 *
 * NB: These values are intentionally assigned for
 *     direct use when setting up h/w descriptors.
 */
typedef enum {
	HAL_PKT_TYPE_NORMAL 		= 0,
	HAL_PKT_TYPE_ATIM 		= 1,
	HAL_PKT_TYPE_PSPOLL 		= 2,
	HAL_PKT_TYPE_BEACON 		= 3,
	HAL_PKT_TYPE_PROBE_RESP 	= 4,
	HAL_PKT_TYPE_PIFS 		= 5,
//	HAL_PKT_TYPE_CHIRP		= 5,
//	HAL_PKT_TYPE_GRP_POLL 		= 6,
} HAL_PKT_TYPE;

/*
 * Used to compute TX times
 */

#define AR5K_CCK_SIFS_TIME		10
#define AR5K_CCK_PREAMBLE_BITS		144
#define AR5K_CCK_PLCP_BITS		48

#define AR5K_OFDM_SIFS_TIME		16
#define AR5K_OFDM_PREAMBLE_TIME		20
#define AR5K_OFDM_PLCP_BITS		22
#define AR5K_OFDM_SYMBOL_TIME		4

#define AR5K_TURBO_SIFS_TIME		8
#define AR5K_TURBO_PREAMBLE_TIME	14
#define AR5K_TURBO_PLCP_BITS		22
#define AR5K_TURBO_SYMBOL_TIME		4

#define AR5K_XR_SIFS_TIME		16
#define AR5K_XR_PLCP_BITS		22
#define AR5K_XR_SYMBOL_TIME		4

/* CCK */

#define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)

#define AR5K_CCK_PHY_TIME(_sp) (_sp ?					\
	((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) :		\
	(AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))

#define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp)				\
	AR5K_CCK_PHY_TIME(_sp) +					\
	((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) +			\
	AR5K_CCK_SIFS_TIME

/* OFDM */

#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))

#define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps *			\
	AR5K_OFDM_SYMBOL_TIME) / 1000)

#define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))

#define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen)				\
	howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))

#define AR5K_OFDM_TX_TIME(_kbps, _frmlen)				\
	AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME +			\
	(AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)

/* TURBO */

#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))

#define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) *		\
	AR5K_TURBO_SYMBOL_TIME) / 1000)

#define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))

#define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen)				\
	howmany(AR5K_TURBO_NUM_BITS(_frmlen),				\
	AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))

#define AR5K_TURBO_TX_TIME(_kbps, _frmlen)				\
	AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME +		\
	(AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)

/* eXtendent Range (?)*/

#define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)

#define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps *			\
	AR5K_XR_SYMBOL_TIME) / 1000)

#define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))

#define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen)				\
	howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))

#define AR5K_XR_TX_TIME(_kbps, _frmlen)					\
	AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME +		\
	(AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)

/*
 * RX definitions
 */

/* Rx Filter Frame Types */
#define	HAL_RX_FILTER_UCAST 		0x00000001	/* Allow unicast frames */
#define	HAL_RX_FILTER_MCAST 		0x00000002	/* Allow multicast frames */
#define	HAL_RX_FILTER_BCAST 		0x00000004	/* Allow broadcast frames */
#define	HAL_RX_FILTER_CONTROL 		0x00000008	/* Allow control frames */
#define	HAL_RX_FILTER_BEACON 		0x00000010	/* Allow beacon frames */
#define	HAL_RX_FILTER_PROM 		0x00000020	/* Promiscuous mode */
#define	HAL_RX_FILTER_XRPOLL 		0x00000040	/* Allow XR poll frmae */
#define	HAL_RX_FILTER_PROBEREQ 		0x00000080	/* Allow probe request frames */
#define	HAL_RX_FILTER_PHYERR 		0x00000100	/* Allow phy errors */
#define	HAL_RX_FILTER_PHYRADAR 		0x00000200	/* Allow phy radar errors*/

typedef struct {
	u_int32_t	ackrcv_bad;
	u_int32_t	rts_bad;
	u_int32_t	rts_good;
	u_int32_t	fcs_bad;
	u_int32_t	beacons;
} HAL_MIB_STATS;

/*
 * Beacon/AP definitions
 */

#define HAL_BEACON_PERIOD	0x0000ffff
#define HAL_BEACON_ENA		0x00800000
#define HAL_BEACON_RESET_TSF	0x01000000

/*
 * Per-station beacon timer state.  Note that the specified
 * beacon interval (given in TU's) can also include flags
 * to force a TSF reset and to enable the beacon xmit logic.
 * If bs_cfpmaxduration is non-zero the hardware is setup to
 * coexist with a PCF-capable AP.
 */