s5335.v

The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the d

//       |         |         |         |         |         |         |        |
// Copyright (C) 2004 - Applied Micro Circuits Corporation
///////////////////////////////////////////////////////////////////////////////
//
//  Title:          Interfacing S5335 chip with the add-On devices 
//                  through Xilinx XC95144XL CPLD
//
//  Author:         S Vargas
//  File:           S5335.v
//
//  Instantiated By: None
//
//  Instantiates:   uc_if.v           ( uc interface module )
//  
//
//  Clock Speeds:   bpclk - 33.0MHz  Master pci clock
//                  clk   - 3.684MHz Microcontroller clock
//  Description:
//    
///////////////////////////////////////////////////////////////////////////////
//
// Revision History:
//   xx/yy/2004    1.0      Initial release
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns


module s5335 (

bpclk,      // Buffered PCI Bus Clock - 33MHz
n_sysrst,   // System wide Reset - ACTIVE LOW
irq,        // General Purpose Interrupt 

// **********  CPLD Interfacing S5335 Register Access  **********
n_be,       // Pass-thru byte enable for dq bus. BE3# = dq[31:24], etc.
n_select,   // active low, enables the S5335 add-On interface
n_rd,       // Reads from S5335 reg.
n_wr,       // Writes on S5335 registers, size will be determined by BE[3:0]
adr,        // Add-on address registers [6:2]
dq,         // Add-on peripheral's datapath [31:0], bus from/to S5335 
   
// **********  Pass-Thru Control & Access  ******************
n_ptatn,    // Pass_Thru_Attention - data must be written/read to PT Register
n_ptburst,  // Pass_Thru_Burst: current PT-Region is a burst access
ptnum,      // Pass_Thru_Region 0, 1, 2 or 3
ptwr,       // Pass_Thru_Write (0=read, 1=write)
n_ptbe,     // Pass_Thru_Byte_Enable 
n_ptrdy,    // Pass_Thru Ready: asserted low when add-On bus completed a cycle
n_ptadr,    // Pass_Thru_address reg; active low

// **********  Direct FIFO Control & Access ******************
n_wrfifo,   // Directly writes to the FIFO w/out using SELECT#, ADR[6:2] etc
n_rdfifo,   // Directly reads from the FIFO w/out using SELECT#,  ADR[6:2] etc
wrfull,     // Indicates FULL condition of the Add-on to PCI FIFO
rdempty,    // Indicates EMPTY condition of the PCI to Add-on FIFO 
fwe,        // indicate if the Add-on to PCI FIFO is Empty
frf,        // indicate if the Add-on to PCI FIFO is Full
amwen,      // Add-on Bus Mastering Write Enable: 1= enable bus master writes
amren,      // Add-on Bus Mastering Read  Enable: 1= enable bus master reads
n_frc,      // FIFO Read  Clear: Driven Low to Clear the PCI to Add-on FIFO 
n_fwc,      // FIFO Write Clear: Driven Low to Clear the Add-on to PCI FIFO 

// *********** Mailbox Access ****************************
ea,         // EA[7:0] hardware Add-on to PCI mailbox reagister to/from S5335
ea8,        // EA8 is mailbox load clock.

// *********** Add-on Access **********************
n_me,       // Add-on Memory (SRAM) chips [3:0] get selected with low signal
n_mrd,      // Memory Read  Enable (active low)
n_mwr,      // Memory Write Enable (active low) 
mad,        // Memory (SRAM) address bus[16:0]
mr_rst,     // Manual Reset (SW1) input    - Active Low
p_rst,      // Host board reset (PC reset) - Active Low
n_mr,       // This is logic "AND" result of p_rst# and n_mr_rst 
mode,       // Add-on bus selector- When MODE = VCC, dq[15:0] else dq[31:0])

// *********** Microcontroller Interface ***********
uc_ad,      // Multiplexed address/data bus (PA[7:0]) - bidirectional bus
//uc_pb,      // Data bus (PB[3:0])
uc_rd,      // Microcontlloer to cpld - read strobe,  Active Low
uc_wr,      // Microcontlloer to cpld - write strobe, Active Low
uc_ale,     // Address latch enable for the multiplexed bus (PE1)

// *********** Unused Spare Pins *******************
//uc_spr_0,   // Microcontlloer to cpld Reserved Pin - Place holders
//uc_spr_1,   // Microcontlloer to cpld Reserved Pin - Place holders
cpld_spr    // Resereved Pins - Place holders
);

//  S5335 General System Signals **********
    input  bpclk;
    input  n_sysrst;

// Interface to S5335 Pass-Thru Registers
    input  n_ptatn;
    input  n_ptburst;
    input  ptwr;
    input  [1:0] ptnum;
    input  [3:0] n_ptbe;
    output n_ptrdy;
    output n_ptadr;
  
// Interface to S5335 FIFO Registers
    input  wrfull;
    input  rdempty;
    output n_wrfifo;
    output n_rdfifo;

    input  fwe;
    input  frf;
    output amwen;
    output amren;
    output n_frc;
    output n_fwc;

// Interface to S5335 MailBox Registers
    output ea8;
    inout  [7:0] ea;

//  S5335 Registers Interfaces - Pass-Thru, FIFO, MAILBOX ETC
    output n_rd;
    output n_wr;
    output n_select;
    inout  [18:0] dq;
    output [ 6:2] adr;
    output [ 3:0] n_be;

    input  irq;
    output n_mr;
    output mode;
    input  p_rst;
    input  mr_rst;

// Microcontroller to CPLD interface
    inout  [7:0] uc_ad;
//    output [3:0] uc_pb;
//    input  [3:0] uc_pb;
    input  uc_ale;	
    input  uc_rd;
    input  uc_wr;

// SPARE PINS to/from ATMEGA - CPLD
//    output uc_spr_0;
//    output uc_spr_1;
//    input uc_spr_0;
//    input uc_spr_1;

// SPARE PINS from CPLD to Headers 
    output [7:0] cpld_spr;

// Interface to Add-on SRAM Memory
    output [16:0] mad;
    output [ 3:0] n_me;
    output n_mwr;
    output n_mrd;

// *************** Internal registers, wires, and buses ***********************
wire mode;
wire n_mrd;
wire n_mwr;
wire chip_en; 
wire wr_mb3;
wire fifo_dis;
wire n_rdfifo;
wire n_wrfifo;
wire [ 3:0] n_me;
wire [ 7:0] uc_rd_data;
wire [15:0] ao_wr_data;

reg  wr_edge;
reg  rd_edge;

reg  aobe;
reg  ao_be;
reg  ao_rd;
reg  ao_wr;
reg  pt_rd;
reg  pt_wr;
reg  pt_select;
reg  ao_select;
reg  [7:0] uc_addr;
reg  nrdfifo;

// ********** Pass-Thru can only be used when S5335 is a PCI Target **********

// Pass-Thru External SRAM memory write/read
assign n_mwr = ~(  ptwr & !n_rd ) & ( n_rdfifo | !bpclk ); //

//assign n_mrd = ~( !ptwr & !n_ptrdy ) & n_wrfifo;
assign n_mrd = ( pt_select | ptwr ) & n_wrfifo; // make SRAM address controlled

assign n_rd = ao_rd & pt_rd;
assign n_wr = ao_wr & pt_wr;

assign n_select = ao_select & pt_select;

// Forcing all RAMs(32-bits) on a read
assign chip_en  = &n_ptbe[3:0];       
assign fifo_req = n_wrfifo & rdempty;

//    Accessing           write                   read            fifo
assign n_me[3] = ( n_ptbe[3] | ~ptwr ) && ( chip_en | ptwr ) && fifo_req;
assign n_me[2] = ( n_ptbe[2] | ~ptwr ) && ( chip_en | ptwr ) && fifo_req;
assign n_me[1] = ( n_ptbe[1] | ~ptwr ) && ( chip_en | ptwr ) && fifo_req;
assign n_me[0] = ( n_ptbe[0] | ~ptwr ) && ( chip_en | ptwr ) && fifo_req;

// ########## *************** End Pass-Thru Interface ********** ##########

// need to get from uC 8-bit to S5335 16-bits
assign dq = ( !ao_wr ) ? {3'b0,ao_wr_data} : 19'hzzzzz;

// ########## *************** Add-On Interface ********** ##########

// Enableing Add-On as well as the Mailbox Registers
assign n_be[3] = ( mode ) ? uc_addr[1] : ( ( ao_be & aobe ) & n_ptbe[3] );
assign n_be[2] = ( ao_be & aobe ) & n_ptbe[2];
assign n_be[1] = ( ao_be & aobe ) & n_ptbe[1];
assign n_be[0] = ( ao_be & aobe ) & n_ptbe[0];

// Add-On address: selects Operation Registers
assign adr = ( mode ) ? uc_addr[6:2] : 5'b01011;

// ########## *************** End Add-On Interface ********** ##########

// PCI reset or board push button will reset S5335 & uC
assign n_mr = p_rst & mr_rst;

// use for debug or ?
assign cpld_spr[0] = 0;
assign cpld_spr[1] = 0;
assign cpld_spr[2] = irq;
assign cpld_spr[3] = n_ptburst;
assign cpld_spr[4] = dq[18];
assign cpld_spr[5] = dq[17];
assign cpld_spr[6] = dq[1];
assign cpld_spr[7] = dq[0];

//assign uc_pb    = 1;
//assign uc_spr_1 = 1;
//assign uc_spr_0 = 1;