uc_if.v

The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the d

// Copyright (C) 2003 - Applied Micro Circuits Corporation
// EV/CHAR 3086 Project
///////////////////////////////////////////////////////////////////////////////
//
//  Author:         Sergio Vargas
//  File:           uc_if.v
//
///////////////////////////////////////////////////////////////////////////////
//
//  Instantiated By: S5335.v
//
//  Instantiates:   none
//
//  Clock Speeds:
//    clk - 33MHz Master clock
//
//  Description
//  This module will handle the interface between the CPLD and the ATmega8515
//  microcontroller(uC). When the XXX bit of the MCUCR register of the uC is
//  set to 1, Port A is the multiplexed Addr/Data bus and Port B is the upper
//  address bus [15:8]. ALE is used to latch the lower address bus [7:0].
//  unfortunately, ALE is asserted on the falling edge of the clk and is active
//  for one clk cycle - ALE goes away on the falling edge of the next clk
//
//  uc_clk   ____/----\_____/----\_____/----\_____/----\____ (3.6864MHz)
//  ALE      _________/----------\__________________________
//           ---------------\/------------------------------
//  Address  ---------------/\------------------------------
//              prev Adr            Address[15:8]
//
//           ---------------\/------\\\/------------------\/
//  Adr/Dat  ---------------/\------///\------------------/\    WRITE
//              prev Adr      Adr[7:0]       Data[7:0]
//  WR       --------------------------\______/-------------
//
//           ---------------\/-----------\/---------------\/
//  Adr/Dat  ---------------/\-----------/\---------------/\     READ
//           prev Adr          Adr[7:0]       Data[7:0]
//  RD       --------------------------\_______/------------
//
///////////////////////////////////////////////////////////////////////////////
//
//  Revision History:
//    xx/yy/2004    0.1      Initial release
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns

module uc_if (
// Inputs
  uc_clk,        // Clock
  resetn,        // Microcontroller Reset, active low	

//////////////////////////////////// CONTROL SIGNALS TO EXT. DEVICES //////////
///// Microcontroller interface
  uc_rd,        // System Read
  uc_wr,        // System Write
  uc_addr,      // System Address Bus
  uc_wr_data,   // data to be sent to uC  
  uc_rd_data,   // data check of CPLD registers	   
  wrfull,       // write FIFO full: 0=DMA write request (Add-On to PCI)
  rdempty,      // read FIFO empty: 0=DMA read request (PCI to Add-On)
  fwe,          // FIFO write empty: Add-On to PCI FIFO is empty
  frf,          // FIFO read full: PCI to Add-On FIFO is full
  n_frc,        // FIFO read clear:
  n_fwc,        // FIFO write clear:
  wr_mb3,       // toggles ea8 to write mailbox byte 3 data
  amwen,        // Add-On bus mastering Write Enable: 1=enables bus writes
  amren,        // Add-On bus mastering Read Enable: 1=enables bus reads
  mode,         // DQ bus width: 0=32-bit, 1=16-bit
  fifo_dis,     // disables the S5335 direct FIFO access
  mb3_wr_data,  // write to direct mailbox byte 3
  ao_wr_data,   // Add-On write data
  ao_rd_data    // Add-On read data
);

// Define Inputs and Outputs for this Module..

////////////////////////////// External Control Signals ///////////////////////
input  uc_clk;
input  resetn;	
input  uc_rd;
input  uc_wr;
input  [7:0] uc_addr;
input  [7:0] uc_wr_data;
output [7:0] uc_rd_data;

input  wrfull;
input  rdempty;
input  fwe;
input  frf;

output n_frc;
output n_fwc;
output wr_mb3;
output amwen;
output amren;
output mode;
output fifo_dis;
output [7:0] mb3_wr_data;

input  [15:0] ao_rd_data;
output [15:0] ao_wr_data;

//////////////////////////////// Inter_Module Signals Internal /////////////

// Interface to Synthesizer Module synth_clk_select   

////////// ********** DEFINE ALL REGISTERS FOR THIS MODULE **********
reg [7:0] reg1;
reg [7:0] reg4;
reg [7:0] reg5;

reg [7:0] uc_rd_data;
reg [7:0] mb3_wr_data;

// ***** Define all Wires and Internal Buses *****

wire uc_clk;
wire resetn;	
wire uc_rd;
wire uc_wr;
wire [7:0] uc_addr;
wire [7:0] uc_wr_data;

wire amwen    = reg1[0];
wire amren    = reg1[1];
wire n_frc    = reg1[2];
wire n_fwc    = reg1[3];
wire fifo_dis = reg1[4];
wire mode     = reg1[7];

wire [15:0] ao_wr_data = {reg5,reg4};

// ********** CPLD memory map: address decoder  ***************
reg wr_mb3;
always @( posedge uc_clk or negedge resetn ) begin
  if ( !resetn )  begin
    wr_mb3      <= 0;
    reg1        <= 8'h1C;
    reg4        <= 8'h00;
    reg5        <= 8'h00;
    mb3_wr_data <= 8'h00;
   end
  else begin
    if ( uc_wr ) begin
      case ( uc_addr )
        8'h81: reg1  <=  uc_wr_data;
        8'h83: begin
            wr_mb3 <= 1;
            mb3_wr_data <= uc_wr_data;
          end
        8'h84: reg4 <= uc_wr_data;
        8'h85: reg5 <= uc_wr_data;
      endcase
    end   // end if write_cmd
    else if ( uc_rd ) begin
      wr_mb3 <= 0;  // GUI does auto reads, so use that to clear this
      case ( uc_addr )
        8'h81: uc_rd_data <= reg1;
        8'h82: uc_rd_data <= {4'h0,wrfull,rdempty,fwe,frf};
        8'h84: uc_rd_data <= ao_rd_data[7:0];
        8'h85: uc_rd_data <= ao_rd_data[15:8];
        default: uc_rd_data <= 8'h06;        // CPLD version: 0.6
      endcase
    end  // end else if read_cmd
  end  // end else
end  // end always@

endmodule