write_flashcfg_c.c

ccs环境下的FLASH烧写文件

/*   Do *not* directly modify this file.  It was    */
/*   generated by the Configuration Tool; any  */
/*   changes risk being overwritten.                */

/* INPUT write_flash.cdb */

/*  Include Header File  */
#include "write_flashcfg.h"


#pragma CODE_SECTION(CSL_cfgInit,".text:CSL_cfgInit")

/*  Config Structures */
EMIF_Config emifCfg0 = {
    0x0020,        /*  Global Control Register   */
    0x0000,        /*  Global Reset Register   */
    0x2fff,        /*  CE0 Space Control Register 1   */
    0x5fff,        /*  CE0 Space Control Register 2   */
    0x0000,        /*  CE0 Space Control Register 3   */
    0x2fff,        /*  CE1 Space Control Register 1   */
    0x5fff,        /*  CE1 Space Control Register 2   */
    0x0000,        /*  CE1 Space Control Register 3   */
    0x2fff,        /*  CE2 Space Control Register 1   */
    0x5fff,        /*  CE2 Space Control Register 2   */
    0x0000,        /*  CE2 Space Control Register 3   */
    0x1fff,        /*  CE3 Space Control Register 1   */
    0x5fff,        /*  CE3 Space Control Register 2   */
    0x0000,        /*  CE3 Space Control Register 3   */
    0xf948,        /*  SDRAM Control Register 1   */
    0x0080,        /*  SDRAM Period Register   */
    0x0000,        /*  SDRAM Initialization Register   */
    0x03ff         /*  SDRAM Control Register 2   */
};

MCBSP_Config mcbspCfg0 = {
    0x1800,        /*  Serial Port Control Register 1   */
    0x0000,        /*  Serial Port Control Register 2   */
    0x0700,        /*  Receive Control Register 1   */
    0x0005,        /*  Receive Control Register 2   */
    0x0700,        /*  Transmit Control Register 1   */
    0x0005,        /*  Transmit Control Register 2   */
    0x0063,        /*  Sample Rate Generator Register 1   */
    0x2000,        /*  Sample Rate Generator Register 2   */
    0x0000,        /*  Multichannel Control Register 1   */
    0x0000,        /*  Multichannel Control Register 2   */
    0x0a0d,        /*  Pin Control Register   */
    0x0000,        /*  Receive Channel Enable Register Partition A   */
    0x0000,        /*  Receive Channel Enable Register Partition B   */
    0x0000,        /*  Receive Channel Enable Register Partition C   */
    0x0000,        /*  Receive Channel Enable Register Partition D   */
    0x0000,        /*  Receive Channel Enable Register Partition E   */
    0x0000,        /*  Receive Channel Enable Register Partition F   */
    0x0000,        /*  Receive Channel Enable Register Partition G   */
    0x0000,        /*  Receive Channel Enable Register Partition H   */
    0x0000,        /*  Transmit Channel Enable Register Partition A   */
    0x0000,        /*  Transmit Channel Enable Register Partition B   */
    0x0000,        /*  Transmit Channel Enable Register Partition C   */
    0x0000,        /*  Transmit Channel Enable Register Partition D   */
    0x0000,        /*  Transmit Channel Enable Register Partition E   */
    0x0000,        /*  Transmit Channel Enable Register Partition F   */
    0x0000,        /*  Transmit Channel Enable Register Partition G   */
    0x0000         /*  Transmit Channel Enable Register Partition H   */
};

PLL_Config pllCfg0 = {
    0x0000,        /*  PLL Response After Idle (IAI)   */
    0x0000,        /*  Response to Loss of PLL Core Lock (IOB)   */
    0x0001,        /*  PLL Multiply Value (PLL_MULT)   */
    0x0001         /*  PLL Divide Value (PLL_DIV)   */
};

/*  Handles  */
DMA_Handle hDma0;
MCBSP_Handle hMcbsp0;

/*
 *  ======== CSL_cfgInit() ========  
 */
void CSL_cfgInit()
{
        hDma0 = DMA_open(DMA_CHA0, DMA_OPEN_RESET);
    hMcbsp0 = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
        
    EMIF_config(&emifCfg0);
    MCBSP_config(hMcbsp0, &mcbspCfg0);
    PLL_config(&pllCfg0);

    /* You must use DMA_start() in your main code to start the DMA. */

	
    
    /* You must use MCBSP_start() in your main code to start the MCBSP. */

    
    /* You must use RTC_start() in your main code to start the RTC. */

    
    /* You must use WDTIM_start() in your main code to start the WDTIM. */

}