📄 sm_pc.c
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#include "Uart.h"
#define FPGA_RD_RR0_Addr (*(volatile unsigned short *)0x08000000)
#define FPGA_RD_RR1_Addr (*(volatile unsigned short *)0x08000002)
#define FPGA_RD_RR2_Addr (*(volatile unsigned short *)0x08000004)
#define FPGA_RD_RR3_Addr (*(volatile unsigned short *)0x08000006)
#define FPGA_RD_RR4_Addr (*(volatile unsigned short *)0x08000008)
#define FPGA_RD_RR5_Addr (*(volatile unsigned short *)0x0800000a)
#define FPGA_RD_RR6_Addr (*(volatile unsigned short *)0x0800000c)
#define FPGA_RD_RR7_Addr (*(volatile unsigned short *)0x0800000e)
#define FPGA_RD_WR0_Addr (*(volatile unsigned short *)0x08000010)
#define FPGA_RD_WR1_Addr (*(volatile unsigned short *)0x08000012)
#define FPGA_RD_WR2_Addr (*(volatile unsigned short *)0x08000014)
#define FPGA_RD_WR3_Addr (*(volatile unsigned short *)0x08000016)
#define FPGA_RD_WR4_Addr (*(volatile unsigned short *)0x08000018)
#define FPGA_RD_WR5_Addr (*(volatile unsigned short *)0x0800001a)
#define FPGA_RD_WR6_Addr (*(volatile unsigned short *)0x0800001c)
#define FPGA_RD_WR7_Addr (*(volatile unsigned short *)0x0800001e)
#define FPGA_WR_WR0_Addr (*(volatile unsigned short *)0x08000000)
#define FPGA_WR_WR1_Addr (*(volatile unsigned short *)0x08000002)
#define FPGA_WR_WR2_Addr (*(volatile unsigned short *)0x08000004)
#define FPGA_WR_WR3_Addr (*(volatile unsigned short *)0x08000006)
#define FPGA_WR_WR4_Addr (*(volatile unsigned short *)0x08000008)
#define FPGA_WR_WR5_Addr (*(volatile unsigned short *)0x0800000a)
#define FPGA_WR_WR6_Addr (*(volatile unsigned short *)0x0800000c)
#define FPGA_WR_WR7_Addr (*(volatile unsigned short *)0x0800000e)
#define FPGA_WR_WR8_Addr (*(volatile unsigned short *)0x08000010)
#define FPGA_WR_WR9_Addr (*(volatile unsigned short *)0x08000012)
#define FPGA_WR_WR10_Addr (*(volatile unsigned short *)0x08000014)
#define FPGA_WR_WR11_Addr (*(volatile unsigned short *)0x08000016)
#define FPGA_WR_WR12_Addr (*(volatile unsigned short *)0x08000018)
#define FPGA_WR_WR13_Addr (*(volatile unsigned short *)0x0800001a)
#define FPGA_WR_WR14_Addr (*(volatile unsigned short *)0x0800001c)
#define FPGA_WR_WR15_Addr (*(volatile unsigned short *)0x0800001e)
int BusWidth=16;
int atoi(char *pstr)
{ int n,NBase,sig;
char *pstr_back;
pstr_back = pstr;
if(*pstr == '\0' ) return(-1);
while(*pstr == ' ' || *pstr == '=' || *pstr == '.' ) pstr++;
NBase = 10;
sig = 1;
if( *pstr == '-' ) { pstr++; sig = -1; }
if( *pstr == '0' ) pstr++;
if( *pstr == 'x' || *pstr == 'X' )
{ pstr++;
NBase = 16;
}
n = 0;
while(1)
{ if ( *pstr >= '0' && *pstr <= '9' )
n = n*NBase + (*pstr - '0');
else if( *pstr >= 'a' && *pstr <= 'f' )
n = n*NBase + (*pstr - 'a')+10;
else if( *pstr >= 'A' && *pstr <= 'F' )
n = n*NBase + (*pstr - 'A')+10;
else
break;
pstr++;
}
pstr = pstr_back;
return(n*sig);
}
unsigned short Read_FPGA(int NumRR)
{ volatile unsigned short RV;
unsigned char HighByte,LowByte;
if(BusWidth==8)
{
switch (NumRR)
{ case 0: LowByte = FPGA_RD_RR0_Addr; HighByte = FPGA_RD_RR1_Addr; break;
case 1: LowByte = FPGA_RD_RR2_Addr; HighByte = FPGA_RD_RR3_Addr; break;
case 2: LowByte = FPGA_RD_RR4_Addr; HighByte = FPGA_RD_RR5_Addr; break;
case 3: LowByte = FPGA_RD_RR6_Addr; HighByte = FPGA_RD_RR7_Addr; break;
case 4: LowByte = FPGA_RD_WR0_Addr; HighByte = FPGA_RD_WR1_Addr; break;
case 5: LowByte = FPGA_RD_WR2_Addr; HighByte = FPGA_RD_WR3_Addr; break;
case 6: LowByte = FPGA_RD_WR4_Addr; HighByte = FPGA_RD_WR5_Addr; break;
case 7: LowByte = FPGA_RD_WR6_Addr; HighByte = FPGA_RD_WR7_Addr; break;
default : LowByte = 255; HighByte = 255; break;
}
RV = (HighByte<<8) + LowByte;
}
else
{
switch (NumRR)
{ case 0: RV = FPGA_RD_RR0_Addr; break;
case 1: RV = FPGA_RD_RR1_Addr; break;
case 2: RV = FPGA_RD_RR2_Addr; break;
case 3: RV = FPGA_RD_RR3_Addr; break;
case 4: RV = FPGA_RD_RR4_Addr; break;
case 5: RV = FPGA_RD_RR5_Addr; break;
case 6: RV = FPGA_RD_RR6_Addr; break;
case 7: RV = FPGA_RD_RR7_Addr; break;
case 10: RV = FPGA_RD_WR0_Addr; break;
case 11: RV = FPGA_RD_WR1_Addr; break;
case 12: RV = FPGA_RD_WR2_Addr; break;
case 13: RV = FPGA_RD_WR3_Addr; break;
case 14: RV = FPGA_RD_WR4_Addr; break;
case 15: RV = FPGA_RD_WR5_Addr; break;
case 16: RV = FPGA_RD_WR6_Addr; break;
case 17: RV = FPGA_RD_WR7_Addr; break;
default : break;
}
}
return(RV);
}
void Write_FPGA(int NumWR,unsigned short NValue)
{
unsigned short HighByte,LowByte;
if(BusWidth==8)
{
HighByte = NValue / 256;
LowByte = NValue % 256;
switch (NumWR)
{
case 0: FPGA_WR_WR1_Addr = HighByte; FPGA_WR_WR0_Addr = LowByte; break;
case 1: FPGA_WR_WR3_Addr = HighByte; FPGA_WR_WR2_Addr = LowByte; break;
case 2: FPGA_WR_WR5_Addr = HighByte; FPGA_WR_WR4_Addr = LowByte; break;
case 3: FPGA_WR_WR7_Addr = HighByte; FPGA_WR_WR6_Addr = LowByte; break;
case 4: FPGA_WR_WR9_Addr = HighByte; FPGA_WR_WR8_Addr = LowByte; break;
case 5: FPGA_WR_WR11_Addr= HighByte; FPGA_WR_WR10_Addr= LowByte; break;
case 6: FPGA_WR_WR13_Addr= HighByte; FPGA_WR_WR12_Addr= LowByte; break;
case 7: FPGA_WR_WR15_Addr= HighByte; FPGA_WR_WR14_Addr= LowByte; break;
default : break;
}
}
else
{
switch (NumWR)
{
case 0: FPGA_WR_WR0_Addr = NValue; break;
case 1: FPGA_WR_WR1_Addr = NValue; break;
case 2: FPGA_WR_WR2_Addr = NValue; break;
case 3: FPGA_WR_WR3_Addr = NValue; break;
case 4: FPGA_WR_WR4_Addr = NValue; break;
case 5: FPGA_WR_WR5_Addr = NValue; break;
case 6: FPGA_WR_WR6_Addr = NValue; break;
case 7: FPGA_WR_WR7_Addr = NValue; break;
default : break;
}
}
return;
}
void TestPcSerialControl(void )
{
char c;
char Str[20];
char *pStr;
int Data,Reg_RR;
int start,write,read,set;
int AxisNo,RegNo;
int AxisNr,RegNr;
int nTime;
SerialPrintf( "\n\n现在处于与PC机联机通讯状态\n");
SerialPrintf( "用户可以通过PC机上的应用程序SMP860_TEST对SMP860板进行测试\n");
SerialPrintf( "按'q'或'Q'键退出...... \n");
start = 0;
AxisNo = 0;
while (c!='Q' && c!='q')
{
c = SerialGetChar(0);
switch(c)
{
case '$':
start = 1;
write = 0;
read = 0;
set = 0;
pStr = Str;
*pStr='\0';
break;
case 'W':
if(start)
write = 1;
break;
case 'R':
if(start)
read = 1;
break;
case 'S':
if(start)
set = 1;
break;
case '#':
if(start)
{
/*
pStr--;
RegNo= *pStr -'0';
pStr = Str;
*/
pStr = Str;
RegNo = atoi(pStr);
//SerialPrintf( "RegNo=%d\n",RegNo ) ;
}
break;
case '*':
if(start)
{
pStr = Str;
Data = atoi(pStr);
//SerialPrintf( "Data=%d\n",Data ) ;
if(write)
if(RegNo == 9)
{
if(Data == 8)
BusWidth = 8;
else
BusWidth = 16;
}
else
{
Write_FPGA(RegNo,Data);
if (Data>2048) AxisNo =3;
else if(Data>1024) AxisNo =2;
else if(Data> 512) AxisNo =1;
else AxisNo =0;
//SerialPrintf( "$Write_FPGA(%d,%d,%s)!",RegNo,Data,Str );
}
else if(read)
{
if(RegNo>=20 && RegNo<=23 ) // LP,EP,CV,CA
{
Reg_RR = Read_FPGA(7);
Reg_RR <<= 16;
Reg_RR += Read_FPGA(6);
SerialPrintf( "$%1d%02d#%d*",AxisNo,RegNo,Reg_RR);
}
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