📄 start_gcc.s
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/*
* file:
* start.S
* description:
* s3c44b0 startup code.
*/
/* MEMORY AREA */
#define _RAM_STARTADDRESS 0x0c000000
#define _RAM_ENDADDRESS 0x0c800000
#define _ROM_STARTADDRESS 0x00000000
#define _ROM_ENDADDRESS 0x00200000
/* STACK DEFINITIONS */
#define _FIQ_STACK_ADDRESS (_RAM_ENDADDRESS-0x00000) /* 14K */
#define _IRQ_STACK_ADDRESS (_RAM_ENDADDRESS-0x03800) /* 14K */
#define _ABT_STACK_ADDRESS (_RAM_ENDADDRESS-0x07000) /* 1K */
#define _SVC_STACK_ADDRESS (_RAM_ENDADDRESS-0x07400) /* 2K */
#define _UND_STACK_ADDRESS (_RAM_ENDADDRESS-0x07c00) /* 1k */
#define _USR_STACK_ADDRESS (_RAM_ENDADDRESS-0x08000) /* 0K */
/* PROCESSOR MODE */
#define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */
#define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */
#define ABT_MODE 0x17 /* Abort Mode(ABT) */
#define SVC_MODE 0x13 /* Supervisor Mode (SVC) */
#define UND_MODE 0x1b /* Undefine Mode(UDF) */
#define USR_MODE 0x10 /* User Mode(USR) */
#define SYS_MODE 0x1f /* System Mode(SYS) */
#define MODE_MSK 0x1f /* Processor Mode Mask */
/* IRQ BITS */
#define F_BIT 0x40 /* FIQ Disable */
#define I_BIT 0x80 /* IRQ Disable */
#define LOCKOUT 0xc0 /* Interrupt lockout mask value */
/* WATCHDOG TIMER SPECIAL REGISTERS */
#define WTCON 0x01d30000
#define WTDAT 0x01d30004
#define WTCNT 0x01d30008
/* INTERRUPT CONTROLLER SPECIAL REGISTERS */
#define INTCON 0x01e00000
#define INTPND 0x01e00004
#define INTMOD 0x01e00008
#define INTMSK 0x01e0000c
#define I_ISPR 0x01e00020
#define I_ISPC 0x01e00024
/* CPU WRAPPER SPECIAL REGISTERS */
#define SYSCFG 0x01c00000
#define NCACHBE0 0x01c00004
#define NCACHBE1 0x01c00008
#define SBUSCON 0x01c40000
/* CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER */
#define PLLCON 0x01d80000
#define CLKCON 0x01d80004
#define CLKSLOW 0x01d80008
#define LOCKTIME 0x01d8000c
#define M_DIV 56 /* Fin= 8MHz Fout=64MHz */
#define P_DIV 2
#define S_DIV 1
/*
#define M_DIV 52 ; Fin=10MHz Fout=60MHz
#define P_DIV 3
#define S_DIV 1
*/
/* MEMORY CONTROLLER SPECIAL REGISGERS */
#define BWSCON 0x01c80000
#define BANKCON0 0x01c80004
#define BANKCON1 0x01c80008
#define BANKCON2 0x01c8000c
#define BANKCON3 0x01c80010
#define BANKCON4 0x01c80014
#define BANKCON5 0x01c80018
#define BANKCON6 0x01c8001c
#define BANKCON7 0x01c80020
#define REFRESH 0x01c80024
#define BANKSIZE 0x01c80028
#define MRSRB6 0x01c8002c
#define MRSRB7 0x01c80030
/* NON-CACHEABLE AREA CONTROL REGISTER (NCACHBEn) */
#define NCACHESTART 0x00000000 /* Non cache area start adddress 0x00000000 */
#define NCACHEEND 0xc0000000 /* Non cache area end address 0x0c000000 */
/* STARTUP CODE */
.text
.global _start
_start:
b SystemResetHandler
ldr pc, =_RAM_STARTADDRESS+4 /* b SystemUndefinedHandler */
ldr pc, =_RAM_STARTADDRESS+8 /* b SystemSwiHandler */
ldr pc, =_RAM_STARTADDRESS+12 /* b SystemPrefetchHandler */
ldr pc, =_RAM_STARTADDRESS+16 /* b SystemAbortHandler */
ldr pc, =_RAM_STARTADDRESS+20 /* b SystemReservedHandler */
ldr pc, =_RAM_STARTADDRESS+24 /* b SystemIrqHandler */
ldr pc, =_RAM_STARTADDRESS+28 /* b SystemFiqHandler */
.ltorg
ConfigMemoryData:
.word 0x11111112 /* BWSCON */
.word 0x00000600 /* GCS0 */
.word 0x00007ffc /* GCS1 */
.word 0x00007ffc /* GCS2 */
.word 0x00007ffc /* GCS3 */
.word 0x00007ffc /* GCS4 */
.word 0x00007ffc /* GCS5 */
.word 0x00018000 /* GCS6, SDRAM (MT = 11, Trcd = 0, SCAN = 0) */
.word 0x00018000 /* GCS7, SDRAM (MT = 11, Trcd = 0, SCAN = 0) */
#if M_DIV == 56
.word 0x00800000+1050
#endif
#if M_DIV == 52
.word 0x00800000+1113
#endif
/* Refresh(REFEN=1, TREFMD=0, Trp=2, Trc=5, Tchr=3) */
/* If refresh period is 15.6 us and MCLK is 60 MHz, */
/* the refresh count is as follows; */
/* refresh count = 2^11 + 1 - 60x15.6 = 1113 */
.word 0x10 /* SCLK power down mode, BankSize 32M/32M */
.word 0x20 /* MRSR 6(CL=2) */
.word 0x20 /* MRSR 7(CL=2) */
SystemReservedHandler:
b SystemReservedHandler
SystemResetHandler:
ldr r0, =WTCON
ldr r1, =0x8000
str r1,[r0]
ldr r0, =INTCON
ldr r1, =0x07
str r1, [r0]
ldr r0, =INTMOD
ldr r1, =0x00
str r1, [r0]
ldr r0, =INTMSK
ldr r1, =0x07ffffff
str r1, [r0]
ldr r0, =I_ISPC
ldr r1, =0x03ffffff
str r1, [r0]
ldr r0, =SYSCFG
ldr r1, =0x00
str r1, [r0]
ldr r0, =NCACHBE0
ldr r1, =NCACHESTART | NCACHEEND
str r1, [r0]
ldr r0, =NCACHBE1
ldr r1, =0x00
str r1, [r0]
b Initialize_Memory
.ltorg
Initialize_Memory:
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
ldr r0, =ConfigMemoryData
sublt r0, r0, r1
ldmia r0, {r1-r13}
ldr r0, =BWSCON
stmia r0, {r1-r13}
b Initialize_Code
.ltorg
.extern Image_RO_Base
.extern Image_RO_Limit
.extern Image_RW_Base
.extern Image_RW_Limit
.extern Image_ZI_Base
.extern Image_ZI_Limit
Initialize_Code:
mov r0, pc
ldr r1, =_RAM_STARTADDRESS
cmp r0, r1
bge Initialize_Clock
ldr r0, =_ROM_STARTADDRESS
ldr r1, =_start
ldr r2, =Image_ZI_Base
code0:
cmp r1, r2
bge code1
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
b code0
code1:
ldr pc, =_RAM_STARTADDRESS
.ltorg
Initialize_Clock:
ldr r0, =LOCKTIME
ldr r1, =0x0fff
str r1, [r0]
ldr r0, =PLLCON
ldr r1, =((M_DIV<<12)+(P_DIV<<4)+S_DIV)
str r1, [r0]
ldr r0, =CLKCON
ldr r1, =0x7ff8
str r1,[r0]
b Initialize_Vector
.ltorg
Initialize_Vector:
ldr r0, =_RAM_STARTADDRESS;
add r0, r0, #4
ldr r1, =SystemUndefinedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemSwiHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemPrefetchHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemAbortHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemReservedHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemIrqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
add r0, r0, #4
ldr r1, =SystemFiqHandler
sub r1, r1, #8
sub r1, r1, r0
mov r1, r1, lsr#2
orr r1, r1, #0xea000000
str r1, [r0]
b Initialize_Stack
.ltorg
Initialize_Stack:
mov r0, #0x00
orr r1, r0, #LOCKOUT|FIQ_MODE
msr cpsr_all, r1
ldr sp, =_FIQ_STACK_ADDRESS
orr r1, r0, #I_BIT|IRQ_MODE
msr cpsr_all, r1
ldr sp, =_IRQ_STACK_ADDRESS
orr r1, r0, #LOCKOUT|ABT_MODE
msr cpsr_all, r1
ldr sp, =_ABT_STACK_ADDRESS
orr r1, r0, #LOCKOUT|UND_MODE
msr cpsr_all, r1
ldr sp, =_UND_STACK_ADDRESS
orr r1, r0, #LOCKOUT|SVC_MODE
msr cpsr_all, r1
ldr sp, =_SVC_STACK_ADDRESS
b Initialize_Data
.ltorg
Initialize_Data:
ldr r0, =Image_RO_Limit
ldr r1, =Image_RW_Base
ldr r2, =Image_ZI_Base
ldr r3, =Image_ZI_Limit
mov r4, #0x00
cmp r0, r1
beq data1
data0:
cmp r1, r2
ldrcc r5, [r0], #4
strcc r5, [r1], #4
bcc data0
data1:
cmp r2, r3
strcc r4, [r2], #4
bcc data1
b Initialize_Entry
.ltorg
.extern _os_entry
Initialize_Entry:
mov r0, #SYS_MODE
msr cpsr_all, r0
ldr sp, =_USR_STACK_ADDRESS
bl _os_entry
b .
.ltorg
.extern Isr_UndefineHandler
SystemUndefinedHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_UndefineHandler
ldmfd sp!, {r0-r3, ip, pc}^
.extern Isr_SwiHandler
SystemSwiHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
ldr r1, [r0]
bic r1, r1, #0xff000000
bl Isr_SwiHandler
ldmfd sp!, {r0-r3, ip, pc}^
.extern Isr_PrefetchAbortHandler
SystemPrefetchHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #4
bl Isr_PrefetchAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
.extern Isr_DataAbortHandler
SystemAbortHandler:
stmfd sp!, {r0-r3, ip, lr}
sub r0, lr, #8
bl Isr_DataAbortHandler
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #8
.extern _irq_entry
SystemIrqHandler:
stmfd sp!, {r0-r3, ip, lr}
ldr r1, =I_ISPR
ldr r1, [r1]
cmp r1, #0x00 /* If the IDLE mode work-around is used, r1 may be 0 sometimes. */
beq irq2
mov r0, #0x00
irq0:
movs r1, r1, lsr #1
bcs irq1
add r0, r0, #1
b irq0
irq1:
b _irq_entry
irq2:
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
.ltorg
.extern _irq_entry
SystemFiqHandler:
stmfd sp!, {r0-r3, ip, lr}
ldr r1, =INTPND
ldr r1, [r1]
cmp r1, #0x00 /* If the IDLE mode work-around is used, r1 may be 0 sometimes. */
beq fiq2
mov r0, #0x00
fiq0:
movs r1, r1, lsr #1
bcs fiq1
add r0, r0, #1
b fiq0
fiq1:
b _irq_entry
fiq2:
ldmfd sp!, {r0-r3, ip, lr}
subs pc, lr, #4
.ltorg
.end
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