iomx8.h

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#define PCINT4    4
#define PCINT3    3
#define PCINT2    2
#define PCINT1    1
#define PCINT0    0

#define PCMSK1  _SFR_MEM8 (0x6C)
/* PCMSK1 */
#define PCINT14   6
#define PCINT13   5
#define PCINT12   4
#define PCINT11   3
#define PCINT10   2
#define PCINT9    1
#define PCINT8    0

#define PCMSK2  _SFR_MEM8 (0x6D)
/* PCMSK2 */
#define PCINT23   7
#define PCINT22   6
#define PCINT21   5
#define PCINT20   4
#define PCINT19   3
#define PCINT18   2
#define PCINT17   1
#define PCINT16   0

#define TIMSK0  _SFR_MEM8 (0x6E)
/* TIMSK0 */
#define OCIE0B  2
#define OCIE0A  1
#define TOIE0   0

#define TIMSK1  _SFR_MEM8 (0x6F)
/* TIMSK1 */
#define ICIE1   5
#define OCIE1B  2
#define OCIE1A  1
#define TOIE1   0

#define TIMSK2  _SFR_MEM8 (0x70)
/* TIMSK2 */
#define OCIE2B  2
#define OCIE2A  1
#define TOIE2   0

#ifndef __ASSEMBLER__
#define ADC     _SFR_MEM16 (0x78)
#endif
#define ADCW    _SFR_MEM16 (0x78)
#define ADCL    _SFR_MEM8 (0x78)
#define ADCH    _SFR_MEM8 (0x79)

#define ADCSRA  _SFR_MEM8 (0x7A)
/* ADCSRA */
#define ADEN    7
#define ADSC    6
#define ADATE   5
#define ADIF    4
#define ADIE    3
#define ADPS2   2
#define ADPS1   1
#define ADPS0   0

#define ADCSRB  _SFR_MEM8 (0x7B)
/* ADCSRB */
#define ACME    6
#define ADTS2   2
#define ADTS1   1
#define ADTS0   0

#define ADMUX   _SFR_MEM8 (0x7C)
/* ADMUX */
#define REFS1   7
#define REFS0   6
#define ADLAR   5
#define MUX3    3
#define MUX2    2
#define MUX1    1
#define MUX0    0

#define DIDR0   _SFR_MEM8 (0x7E)
/* DIDR0 */
#define ADC5D   5
#define ADC4D   4
#define ADC3D   3
#define ADC2D   2
#define ADC1D   1
#define ADC0D   0

#define DIDR1   _SFR_MEM8 (0x7F)
/* DIDR1 */
#define AIN1D   1
#define AIN0D   0

#define TCCR1A  _SFR_MEM8 (0x80)
/* TCCR1A */
#define COM1A1  7
#define COM1A0  6
#define COM1B1  5
#define COM1B0  4
#define WGM11   1
#define WGM10   0

#define TCCR1B  _SFR_MEM8 (0x81)
/* TCCR1B */
#define ICNC1   7
#define ICES1   6
#define WGM13   4
#define WGM12   3
#define CS12    2
#define CS11    1
#define CS10    0

#define TCCR1C  _SFR_MEM8 (0x82)
/* TCCR1C */
#define FOC1A   7
#define FOC1B   6

#define TCNT1   _SFR_MEM16 (0x84)
#define TCNT1L  _SFR_MEM8 (0x84)
#define TCNT1H  _SFR_MEM8 (0x85)

#define ICR1    _SFR_MEM16 (0x86)
#define ICR1L   _SFR_MEM8 (0x86)
#define ICR1H   _SFR_MEM8 (0x87)

#define OCR1A   _SFR_MEM16 (0x88)
#define OCR1AL  _SFR_MEM8 (0x88)
#define OCR1AH  _SFR_MEM8 (0x89)

#define OCR1B   _SFR_MEM16 (0x8A)
#define OCR1BL  _SFR_MEM8 (0x8A)
#define OCR1BH  _SFR_MEM8 (0x8B)

#define TCCR2A  _SFR_MEM8 (0xB0)
/* TCCR2A */
#define COM2A1  7
#define COM2A0  6
#define COM2B1  5
#define COM2B0  4
#define WGM21   1
#define WGM20   0

#define TCCR2B  _SFR_MEM8 (0xB1)
/* TCCR2B */
#define FOC2A   7
#define FOC2B   6
#define WGM22   3
#define CS22    2
#define CS21    1
#define CS20    0

#define TCNT2   _SFR_MEM8 (0xB2)
#define OCR2A   _SFR_MEM8 (0xB3)
#define OCR2B   _SFR_MEM8 (0xB4)

#define ASSR    _SFR_MEM8 (0xB6)
/* ASSR */
#define EXCLK    6
#define AS2      5
#define TCN2UB   4
#define OCR2AUB  3
#define OCR2BUB  2
#define TCR2AUB  1
#define TCR2BUB  0

#define TWBR    _SFR_MEM8 (0xB8)

#define TWSR    _SFR_MEM8 (0xB9)
/* TWSR */
#define TWS7    7
#define TWS6    6
#define TWS5    5
#define TWS4    4
#define TWS3    3
#define TWPS1   1
#define TWPS0   0

#define TWAR    _SFR_MEM8 (0xBA)
/* TWAR */
#define TWA6    7
#define TWA5    6
#define TWA4    5
#define TWA3    4
#define TWA2    3
#define TWA1    2
#define TWA0    1
#define TWGCE   0

#define TWDR    _SFR_MEM8 (0xBB)

#define TWCR    _SFR_MEM8 (0xBC)
/* TWCR */
#define TWINT   7
#define TWEA    6
#define TWSTA   5
#define TWSTO   4
#define TWWC    3
#define TWEN    2
#define TWIE    0

#define TWAMR   _SFR_MEM8 (0xBD)
/* TWAMR */
#define TWAM6   7
#define TWAM5   6
#define TWAM4   5
#define TWAM3   4
#define TWAM2   3
#define TWAM1   2
#define TWAM0   1

#define UCSR0A  _SFR_MEM8 (0xC0)
/* UCSR0A */
#define RXC0    7
#define TXC0    6
#define UDRE0   5
#define FE0     4
#define DOR0    3
#define UPE0    2
#define U2X0    1
#define MPCM0   0

#define UCSR0B  _SFR_MEM8 (0xC1)
/* UCSR0B */
#define RXCIE0  7
#define TXCIE0  6
#define UDRIE0  5
#define RXEN0   4
#define TXEN0   3
#define UCSZ02  2
#define RXB80   1
#define TXB80   0

#define UCSR0C  _SFR_MEM8 (0xC2)
/* UCSR0C */
#define UMSEL01  7
#define UMSEL00  6
#define UPM01    5
#define UPM00    4
#define USBS0    3
#define UCSZ01   2
#define UDORD0   2
#define UCSZ00   1
#define UCPHA0   1
#define UCPOL0   0

#define UBRR0   _SFR_MEM16 (0xC4)
#define UBRR0L  _SFR_MEM8 (0xC4)
#define UBRR0H  _SFR_MEM8 (0xC5)
#define UDR0    _SFR_MEM8 (0xC6)

/* Interrupt vectors */

/* External Interrupt Request 0 */
#define INT0_vect			_VECTOR(1)
#define SIG_INTERRUPT0			_VECTOR(1)

/* External Interrupt Request 1 */
#define INT1_vect			_VECTOR(2)
#define SIG_INTERRUPT1			_VECTOR(2)

/* Pin Change Interrupt Request 0 */
#define PCINT0_vect			_VECTOR(3)
#define SIG_PIN_CHANGE0			_VECTOR(3)

/* Pin Change Interrupt Request 0 */
#define PCINT1_vect			_VECTOR(4)
#define SIG_PIN_CHANGE1			_VECTOR(4)

/* Pin Change Interrupt Request 1 */
#define PCINT2_vect			_VECTOR(5)
#define SIG_PIN_CHANGE2			_VECTOR(5)

/* Watchdog Time-out Interrupt */
#define WDT_vect			_VECTOR(6)
#define SIG_WATCHDOG_TIMEOUT		_VECTOR(6)

/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPA_vect		_VECTOR(7)
#define SIG_OUTPUT_COMPARE2A		_VECTOR(7)

/* Timer/Counter2 Compare Match A */
#define TIMER2_COMPB_vect		_VECTOR(8)
#define SIG_OUTPUT_COMPARE2B		_VECTOR(8)

/* Timer/Counter2 Overflow */
#define TIMER2_OVF_vect			_VECTOR(9)
#define SIG_OVERFLOW2			_VECTOR(9)

/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect		_VECTOR(10)
#define SIG_INPUT_CAPTURE1		_VECTOR(10)

/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect		_VECTOR(11)
#define SIG_OUTPUT_COMPARE1A		_VECTOR(11)

/* Timer/Counter1 Compare Match B */
#define TIMER1_COMPB_vect		_VECTOR(12)
#define SIG_OUTPUT_COMPARE1B		_VECTOR(12)

/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect			_VECTOR(13)
#define SIG_OVERFLOW1			_VECTOR(13)

/* TimerCounter0 Compare Match A */
#define TIMER0_COMPA_vect		_VECTOR(14)
#define SIG_OUTPUT_COMPARE0A		_VECTOR(14)

/* TimerCounter0 Compare Match B */
#define TIMER0_COMPB_vect		_VECTOR(15)
#define SIG_OUTPUT_COMPARE0B		_VECTOR(15)

/* Timer/Couner0 Overflow */
#define TIMER0_OVF_vect			_VECTOR(16)
#define SIG_OVERFLOW0			_VECTOR(16)

/* SPI Serial Transfer Complete */
#define SPI_STC_vect			_VECTOR(17)
#define SIG_SPI				_VECTOR(17)

/* USART Rx Complete */
#define USART_RX_vect			_VECTOR(18)
#define SIG_USART_RECV			_VECTOR(18)

/* USART, Data Register Empty */
#define USART_UDRE_vect			_VECTOR(19)
#define SIG_USART_DATA			_VECTOR(19)

/* USART Tx Complete */
#define USART_TX_vect			_VECTOR(20)
#define SIG_USART_TRANS			_VECTOR(20)

/* ADC Conversion Complete */
#define ADC_vect			_VECTOR(21)
#define SIG_ADC				_VECTOR(21)

/* EEPROM Ready */
#define EE_READY_vect			_VECTOR(22)
#define SIG_EEPROM_READY		_VECTOR(22)

/* Analog Comparator */
#define ANALOG_COMP_vect		_VECTOR(23)
#define SIG_COMPARATOR			_VECTOR(23)

/* Two-wire Serial Interface */
#define TWI_vect			_VECTOR(24)
#define SIG_TWI				_VECTOR(24)
#define SIG_2WIRE_SERIAL		_VECTOR(24)

/* Store Program Memory Read */
#define SPM_READY_vect			_VECTOR(25)
#define SIG_SPM_READY			_VECTOR(25)

/* The mega48 and mega88 vector tables are single instruction entries (16 bits
   per entry for an RJMP) while the mega168 table has double instruction
   entries (32 bits per entry for a JMP). */

#if defined (__AVR_ATmega168__)
#  define _VECTORS_SIZE 104
#else
#  define _VECTORS_SIZE 52
#endif

#endif /* _AVR_IOM8_H_ */