📄 c5mcompc.mdl
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Cell "CustomSymbolStrMacro"
PropName "DisabledProps"
}
Version "1.2.0"
ForceParamTrailComments off
GenerateComments on
IgnoreCustomStorageClasses on
IncHierarchyInIds off
MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 13
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.2.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeERTFirstTime on
ERTFirstTimeCompliant off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType DiscreteZeroPole
Zeros "[1]"
Poles "[0 1]"
Gain "[1]"
SampleTime "1"
StateMustResolveToSignalObject off
RTWStateStorageClass "Auto"
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
SampleTime "-1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType ZeroPole
Zeros "[1]"
Poles "[0 1]"
Gain "[1]"
AbsoluteTolerance "auto"
}
Block {
BlockType ZeroOrderHold
SampleTime "1"
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "c5mcompc"
Location [2, 78, 1022, 747]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "portrait"
PaperPositionMode "auto"
PaperType "a4letter"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "182"
ReportName "simulink-default.rpt"
Block {
BlockType DiscreteZeroPole
Name "Discrete\nZero-Pole"
Position [185, 88, 270, 132]
FontName "Times New Roman"
FontSize 14
Zeros "[z1]"
Poles "[p1]"
Gain "K"
SampleTime "-1"
}
Block {
BlockType Step
Name "Step"
Position [25, 95, 55, 125]
FontName "Times New Roman"
FontSize 14
Time "0"
SampleTime "0"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [80, 100, 100, 120]
ShowName off
FontName "Times New Roman"
FontSize 14
IconShape "round"
Inputs "|+-"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold"
Position [125, 91, 160, 129]
FontName "Times New Roman"
FontSize 14
SampleTime "T"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold1"
Position [295, 91, 330, 129]
FontName "Times New Roman"
FontSize 14
SampleTime "T"
}
Block {
BlockType ZeroOrderHold
Name "Zero-Order\nHold2"
Position [455, 91, 490, 129]
FontName "Times New Roman"
FontSize 14
SampleTime "T"
}
Block {
BlockType ZeroPole
Name "Zero-Pole"
Position [355, 88, 425, 132]
FontName "Times New Roman"
FontSize 14
Zeros "[]"
Poles "[0,-a]"
Gain "a"
}
Block {
BlockType Outport
Name "Out1"
Position [525, 103, 555, 117]
FontName "Times New Roman"
FontSize 14
IconDisplay "Port number"
}
Block {
BlockType Outport
Name "Out2"
Position [525, 53, 555, 67]
FontName "Times New Roman"
FontSize 14
Port "2"
IconDisplay "Port number"
}
Line {
SrcBlock "Step"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Zero-Order\nHold"
DstPort 1
}
Line {
SrcBlock "Zero-Order\nHold"
SrcPort 1
DstBlock "Discrete\nZero-Pole"
DstPort 1
}
Line {
SrcBlock "Discrete\nZero-Pole"
SrcPort 1
DstBlock "Zero-Order\nHold1"
DstPort 1
}
Line {
SrcBlock "Zero-Order\nHold1"
SrcPort 1
DstBlock "Zero-Pole"
DstPort 1
}
Line {
SrcBlock "Zero-Pole"
SrcPort 1
Points [5, 0]
Branch {
DstBlock "Zero-Order\nHold2"
DstPort 1
}
Branch {
Points [0, 65; -345, 0]
DstBlock "Sum"
DstPort 2
}
Branch {
Points [0, -50]
DstBlock "Out2"
DstPort 1
}
}
Line {
SrcBlock "Zero-Order\nHold2"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
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