📄 c6mmr.mdl
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Model {
Name "c6mmr"
Version 5.1
SaveDefaultBlockParams on
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
ShowLoopsOnError on
IgnoreBidirectionalLines off
ShowStorageClass off
SortedOrder off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovMetricSettings "dw"
CovNameIncrementing off
CovHtmlReporting on
covSaveCumulativeToWorkspaceVar on
CovSaveSingleToWorkspaceVar on
CovCumulativeVarName "covCumulativeData"
CovCumulativeReport off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
MinMaxOverflowArchiveMode "Overwrite"
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Thu Jul 31 15:02:30 2003"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "Prof Xue Dingyu"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Tue Sep 20 19:00:09 2005"
ModelVersionFormat "1.%<AutoIncrement:6>"
ConfigurationManager "None"
SimParamPage "Solver"
LinearizationMsg "none"
Profile off
ParamWorkspaceSource "MATLABWorkspace"
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
TryForcingSFcnDF off
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeSkipDownloadWhenConnect off
ExtModeLogAll on
ExtModeAutoUpdateStatusClock on
BufferReuse on
RTWExpressionDepthLimit 5
SimulationMode "normal"
Solver "ode45"
SolverMode "Auto"
StartTime "0.0"
StopTime "10.0"
MaxOrder 5
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
RelTol "1e-3"
AbsTol "auto"
OutputOption "RefineOutputTimes"
OutputTimes "[]"
Refine "1"
LoadExternalInput off
ExternalInput "[t, u]"
LoadInitialState off
InitialState "xInitial"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
Decimation "1"
LimitDataPoints on
MaxDataPoints "1000"
SignalLoggingName "sigsOut"
ConsistencyChecking "none"
ArrayBoundsChecking "none"
AlgebraicLoopMsg "warning"
BlockPriorityViolationMsg "warning"
MinStepSizeMsg "warning"
InheritedTsInSrcMsg "warning"
DiscreteInheritContinuousMsg "warning"
MultiTaskRateTransMsg "error"
SingleTaskRateTransMsg "none"
CheckForMatrixSingularity "none"
IntegerOverflowMsg "warning"
Int32ToFloatConvMsg "warning"
ParameterDowncastMsg "error"
ParameterOverflowMsg "error"
ParameterPrecisionLossMsg "warning"
UnderSpecifiedDataTypeMsg "none"
UnnecessaryDatatypeConvMsg "none"
VectorMatrixConversionMsg "none"
InvalidFcnCallConnMsg "error"
SignalLabelMismatchMsg "none"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
SfunCompatibilityCheckMsg "none"
RTWInlineParameters off
BlockReductionOpt on
BooleanDataType on
ConditionallyExecuteInputs on
ParameterPooling on
OptimizeBlockIOStorage on
ZeroCross on
AssertionControl "UseLocalSettings"
ProdHWDeviceType "Microprocessor"
ProdHWWordLengths "8,16,32,32"
RTWSystemTargetFile "grt.tlc"
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
RTWRetainRTWFile off
TLCProfiler off
TLCDebug off
TLCCoverage off
TLCAssertion off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Abs
SaturateOnIntegerOverflow on
ZeroCross on
}
Block {
BlockType Clock
DisplayTime off
}
Block {
BlockType Integrator
ExternalReset "none"
InitialConditionSource "internal"
InitialCondition "0"
LimitOutput off
UpperSaturationLimit "inf"
LowerSaturationLimit "-inf"
ShowSaturationPort off
ShowStatePort off
AbsoluteTolerance "auto"
ZeroCross on
}
Block {
BlockType Outport
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Product
Inputs "2"
Multiplication "Element-wise(.*)"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType Step
Time "1"
Before "0"
After "1"
VectorParams1D on
ZeroCross on
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
ShowAdditionalParam off
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
}
Block {
BlockType TransferFcn
Numerator "[1]"
Denominator "[1 2 1]"
AbsoluteTolerance "auto"
Realization "auto"
}
Block {
BlockType TransportDelay
DelayTime "1"
InitialInput "0"
BufferSize "1024"
PadeOrder "0"
TransDelayFeedthrough off
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "c6mmr"
Location [249, 133, 999, 426]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "portrait"
PaperPositionMode "auto"
PaperType "a4letter"
PaperUnits "centimeters"
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Abs
Name "Abs"
Position [380, 130, 410, 160]
FontName "Times New Roman"
FontSize 14
}
Block {
BlockType TransportDelay
Name "Delay L"
Position [250, 195, 280, 225]
FontName "Times New Roman"
FontSize 14
DelayTime "L"
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [490, 118, 520, 162]
FontName "Times New Roman"
FontSize 14
}
Block {
BlockType Product
Name "Product"
Ports [2, 1]
Position [440, 120, 465, 155]
ShowName off
FontName "Times New Roman"
FontSize 14
InputSameDT off
}
Block {
BlockType Step
Name "Step"
Position [60, 130, 90, 160]
FontName "Times New Roman"
FontSize 14
Time "0"
SampleTime "0"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [340, 135, 360, 155]
ShowName off
FontName "Times New Roman"
FontSize 14
IconShape "round"
Inputs "|+-"
InputSameDT off
OutDataTypeMode "Inherit via internal rule"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn"
Position [120, 122, 325, 168]
FontName "Times New Roman"
FontSize 14
Denominator "[1 6 15 20 15 6 1]"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn1"
Position [155, 190, 215, 230]
FontName "Times New Roman"
FontSize 14
Numerator "1"
Denominator "[T 1]"
}
Block {
BlockType Clock
Name "time"
Position [360, 90, 380, 110]
FontName "Times New Roman"
FontSize 14
Decimation "10"
}
Block {
BlockType Outport
Name "Out2"
Position [545, 133, 575, 147]
ShowName off
FontName "Times New Roman"
FontSize 14
}
Line {
SrcBlock "Transfer Fcn"
SrcPort 1
DstBlock "Sum"
DstPort 1
}
Line {
SrcBlock "Delay L"
SrcPort 1
Points [65, 0]
DstBlock "Sum"
DstPort 2
}
Line {
SrcBlock "Transfer Fcn1"
SrcPort 1
DstBlock "Delay L"
DstPort 1
}
Line {
SrcBlock "Step"
SrcPort 1
Points [10, 0]
Branch {
DstBlock "Transfer Fcn"
DstPort 1
}
Branch {
Points [0, 65]
DstBlock "Transfer Fcn1"
DstPort 1
}
}
Line {
SrcBlock "Sum"
SrcPort 1
DstBlock "Abs"
DstPort 1
}
Line {
SrcBlock "Abs"
SrcPort 1
DstBlock "Product"
DstPort 2
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
DstBlock "Out2"
DstPort 1
}
Line {
SrcBlock "time"
SrcPort 1
Points [35, 0; 0, 30]
DstBlock "Product"
DstPort 1
}
Annotation {
Position [428, 242]
}
}
}
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