📄 top.rpt
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cpldfit: version G.25a Xilinx Inc.
Fitter Report
Design Name: top Date: 11- 6-2003, 5:13PM
Device Used: XC2C256-5-TQ144
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
200/256 ( 78%) 624 /896 ( 70%) 123/256 ( 48%) 42 /118 ( 36%) 480/640 ( 75%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 2 2 | I/O : 35 73
Output : 30 30 | GCK/IO : 3 0
Bidirectional : 9 9 | GTS/IO : 2 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 | CDR/IO : 1 0
GSR : 0 0 | DGE/IO : 1 0
---- ----
Total 42 42
MACROCELL RESOURCES:
Total Macrocells Available 256
Registered Macrocells 123
Non-registered Macrocell driving I/O 38
GLOBAL RESOURCES:
Signal 'clk' mapped onto global clock net GCK2.
Signal 'N_PZ_1095_MC.GLB' mapped onto global output enable net GTS0.
Global set/reset net(s) unused.
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Slew Pin Pin Pin Reg I/O I/O Reg Init
Name Pt Used Rate # Type Use Use STD Style State
Addr<0> 2 3 FB15_6 (b) (b) TFF RESET
Addr<1> 3 4 FB15_7 (b) (b) TFF RESET
Addr<2> 3 5 FB15_8 (b) (b) TFF RESET
Addr<3> 3 6 FB15_9 (b) (b) TFF RESET
Addr<4> 3 7 FB15_10 (b) (b) TFF RESET
CurrentState_FFD1 21 23 FB3_6 (b) (b) DFF RESET
CurrentState_FFD2 16 17 FB2_8 (b) (b) DFF RESET
CurrentState_FFD3 16 25 FB3_2 135 I/O (b) DFF RESET
CurrentState_FFD4 9 11 FB3_14 132 I/O (b) DFF RESET
CurrentState_FFD5 8 11 FB2_7 (b) (b) DFF RESET
CurrentState_FFD6 10 14 FB2_9 (b) (b) DFF RESET
CurrentState_XX_FFD443 3 13 FB3_5 133 I/O (b)
N_PZ_1001 2 3 FB5_1 (b) (b)
N_PZ_1084 1 2 FB14_1 74 I/O (b)
N_PZ_1086 1 2 FB13_7 (b) (b)
N_PZ_1095 1 3 FB2_5 5 GTS/I/O (b)
N_PZ_1098 1 2 FB15_5 (b) (b)
N_PZ_1142 2 14 FB4_9 (b) (b)
N_PZ_1158 2 3 FB15_4 (b) (b)
N_PZ_1175 1 3 FB15_3 (b) (b)
N_PZ_1179 4 22 FB1_8 (b) (b)
N_PZ_1180 4 23 FB1_9 (b) (b)
N_PZ_1196 2 7 FB7_15 20 I/O (b)
N_PZ_1212 2 6 FB7_14 21 I/O (b)
N_PZ_1276 1 3 FB15_15 91 I/O (b)
N_PZ_1280 3 20 FB4_11 (b) (b)
N_PZ_1292 5 22 FB1_7 (b) (b)
N_PZ_1633 1 2 FB14_3 70 I/O (b)
N_PZ_1634 1 2 FB11_4 (b) (b)
N_PZ_803 1 3 FB5_3 (b) (b)
N_PZ_814 2 10 FB14_10 (b) (b)
N_PZ_838 2 2 FB13_10 (b) (b)
N_PZ_849 3 7 FB11_7 (b) (b)
N_PZ_863 5 6 FB13_11 (b) (b)
N_PZ_919 4 6 FB10_7 (b) (b)
N_PZ_921 4 8 FB5_2 33 I/O (b)
N_PZ_925 6 11 FB13_16 (b) (b)
N_PZ_996 6 12 FB6_4 38 GCK/I/O GCK/I
_n0083 1 24 FB8_12 51 I/O (b)
_n0084 2 7 FB3_8 (b) (b)
addr_clk8 1 3 FB15_1 (b) (b)
ascii_enable 2 6 FB10_8 (b) (b)
conver2ascii_module/CurrentState_FFD1 2 3 FB13_9 (b) (b) DFF RESET
conver2ascii_module/CurrentState_FFD2 2 3 FB13_8 (b) (b) DFF RESET
conver2ascii_module/counter<0> 4 6 FB13_13 81 I/O (b) TFF RESET
conver2ascii_module/counter<1> 3 5 FB13_4 (b) (b) TFF RESET
conver2ascii_module/counter<2> 3 6 FB13_14 82 I/O (b) TFF RESET
conver2ascii_module/counter<3> 4 6 FB13_12 80 I/O (b) DFF RESET
conver2ascii_module/dcount<0> 2 3 FB12_13 96 I/O (b) DFF RESET
conver2ascii_module/dcount<1> 3 4 FB12_12 97 I/O (b) DFF RESET
conver2ascii_module/dcount<2> 3 5 FB12_11 98 I/O (b) TFF RESET
conver2ascii_module/dcount<3> 3 6 FB12_2 100 I/O (b) TFF RESET
conver2ascii_module/dcount<4> 3 7 FB13_1 75 I/O (b) TFF RESET
conver2ascii_module/dcount<5> 3 8 FB14_11 (b) (b) TFF RESET
conver2ascii_module/dcount<6> 3 9 FB14_12 (b) (b) TFF RESET
conver2ascii_module/dcount<7> 3 10 FB14_15 (b) (b) TFF RESET
conver2ascii_module/result_0_0 3 6 FB13_6 79 I/O (b) TFF RESET
conver2ascii_module/result_0_1 3 7 FB13_5 78 I/O (b) TFF RESET
conver2ascii_module/result_0_2 3 8 FB13_3 77 I/O (b) TFF RESET
conver2ascii_module/result_0_3 3 9 FB13_2 76 I/O (b) TFF RESET
counter<0> 2 7 FB3_13 (b) (b) TFF RESET
counter<10> 2 17 FB8_2 45 I/O (b) TFF RESET
counter<11> 2 18 FB8_3 46 I/O (b) TFF RESET
counter<12> 2 19 FB8_5 48 I/O (b) TFF RESET
counter<13> 2 20 FB8_6 49 I/O (b) TFF RESET
counter<14> 2 21 FB8_11 50 I/O (b) TFF RESET
counter<15> 2 22 FB8_13 52 I/O (b) TFF RESET
counter<16> 2 23 FB8_4 (b) (b) TFF RESET
counter<17> 2 24 FB8_7 (b) (b) TFF RESET
counter<18> 2 25 FB8_8 (b) (b) TFF RESET
counter<19> 2 26 FB8_9 (b) (b) TFF RESET
counter<1> 2 8 FB7_3 (b) (b) TFF RESET
counter<20> 2 27 FB8_10 (b) (b) TFF RESET
counter<21> 2 28 FB8_14 (b) (b) TFF RESET
counter<22> 2 29 FB8_15 (b) (b) TFF RESET
counter<23> 2 30 FB8_16 (b) (b) TFF RESET
counter<2> 2 9 FB7_2 (b) (b) TFF RESET
counter<3> 2 10 FB7_1 (b) (b) TFF RESET
counter<4> 2 11 FB7_16 19 I/O (b) TFF RESET
counter<5> 2 12 FB10_13 (b) (b) TFF RESET
counter<6> 2 13 FB10_11 (b) (b) TFF RESET
counter<7> 2 14 FB10_10 (b) (b) TFF RESET
counter<8> 2 15 FB10_9 (b) (b) TFF RESET
counter<9> 2 16 FB8_1 44 I/O (b) TFF RESET
dce 0 0 FB7_12 FAST 23 I/O O LVCMOS33
lcd_db<0> 3 7 FB2_4 FAST 4 I/O O LVCMOS33
lcd_db<1> 2 6 FB2_3 FAST 3 GTS/I/O O LVCMOS33
lcd_db<2> 3 6 FB2_1 FAST 2 GTS/I/O O LVCMOS33
lcd_db<3> 4 6 FB5_6 FAST 30 GCK/I/O O LVCMOS33
lcd_db<4> 3 6 FB5_14 FAST 28 I/O O LVCMOS33
lcd_db<5> 3 6 FB7_5 FAST 26 I/O O LVCMOS33
lcd_db<6> 2 7 FB7_6 FAST 25 I/O O LVCMOS33
lcd_db<7> 3 7 FB7_11 FAST 24 I/O O LVCMOS33
lcd_e 1 16 FB6_1 FAST 34 I/O O LVCMOS33
lcd_module/CurrentState_FFD1 8 19 FB2_11 (b) (b) TFF RESET
lcd_module/CurrentState_FFD2 6 14 FB5_12 (b) (b) DFF RESET
lcd_module/CurrentState_FFD3 6 12 FB2_16 (b) (b) DFF RESET
lcd_module/CurrentState_XX_FFD317 5 15 FB2_10 (b) (b)
lcd_module/DB_reg<0> 16 14 FB10_15 (b) (b) DFF RESET
lcd_module/DB_reg<1> 13 15 FB7_7 (b) (b) DFF RESET
lcd_module/DB_reg<2> 13 17 FB7_4 (b) (b) DFF RESET
lcd_module/DB_reg<3> 12 19 FB5_5 31 I/O (b) DFF RESET
lcd_module/DB_reg<4> 7 14 FB3_9 (b) (b) DFF RESET
lcd_module/DB_reg<5> 8 12 FB7_9 (b) (b) DFF RESET
lcd_module/DB_reg<6> 9 12 FB7_8 (b) (b) DFF RESET
lcd_module/DB_reg<7> 5 10 FB7_10 (b) (b) DFF RESET
lcd_module/_n00153 2 4 FB15_16 92 I/O (b)
lcd_module/bitcounter<0> 2 3 FB5_7 (b) (b) TFF RESET
lcd_module/bitcounter<1> 2 4 FB5_8 (b) (b) TFF RESET
lcd_module/bitcounter<2> 2 5 FB5_9 (b) (b) TFF RESET
lcd_module/bitcounter<3> 2 6 FB5_10 (b) (b) TFF RESET
lcd_module/counter<0> 2 3 FB14_9 (b) (b) DFF RESET
lcd_module/counter<10> 3 13 FB6_5 (b) (b) TFF RESET
lcd_module/counter<11> 3 14 FB6_6 (b) (b) TFF RESET
lcd_module/counter<12> 3 15 FB6_7 (b) (b) TFF RESET
lcd_module/counter<13> 3 16 FB6_8 (b) (b) TFF RESET
lcd_module/counter<14> 3 17 FB6_9 (b) (b) TFF RESET
lcd_module/counter<15> 2 16 FB6_10 (b) (b) TFF RESET
lcd_module/counter<1> 3 4 FB14_8 (b) (b) DFF RESET
lcd_module/counter<2> 3 5 FB14_7 (b) (b) TFF RESET
lcd_module/counter<3> 3 6 FB14_5 (b) (b) TFF RESET
lcd_module/counter<4> 3 7 FB14_16 61 I/O (b) TFF RESET
lcd_module/counter<5> 3 8 FB14_14 64 I/O (b) TFF RESET
lcd_module/counter<6> 3 9 FB14_13 66 I/O (b) TFF RESET
lcd_module/counter<7> 3 10 FB14_6 68 I/O (b) TFF RESET
lcd_module/counter<8> 3 11 FB6_16 43 I/O I TFF RESET
lcd_module/counter<9> 3 12 FB6_3 (b) (b) TFF RESET
lcd_module/power_up_module/CurrentState_FFD1 3 5 FB5_11 (b) (b) DFF RESET
lcd_module/power_up_module/CurrentState_FFD2 4 6 FB5_13 (b) (b) DFF RESET
lcd_module/power_up_module/CurrentState_FFD3 3 6 FB5_16 (b) (b) DFF RESET
lcd_module/power_up_module/CurrentState_FFD4 3 6 FB5_15 (b) (b) DFF RESET
lcd_module/power_up_module/_n00203 1 3 FB14_2 71 I/O (b)
lcd_module/power_up_module/_n0021 1 16 FB6_11 (b) (b)
lcd_rs 1 3 FB6_13 FAST 40 I/O O LVCMOS33
lcd_rw 0 0 FB6_2 FAST 35 CDR/I/O O LVCMOS33
lcd_w 5 10 FB5_4 32 GCK/I/O I
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