top.tim

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                 (Clock: smartcard_module_Bytecounter<5>_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD5_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD4_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD6_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD3_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD2_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                        (Clock: CurrentState_FFD1_MC.Q)

\ From        A     A     A     A
 \            d     d     d     d
  \           d     d     d     d
   \          r     r     r     r
    \         <     <     <     <
     \        0     1     2     3
      \       >     >     >     >
       \      .     .     .     .
        \     Q     Q     Q     Q
  To     \------------------------

Addr<1>.D   3.2                  
Addr<2>.D   3.2   3.2            
Addr<3>.D   3.2   3.2   3.2      
Addr<4>.D   3.2   3.2   3.2   3.2

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                   (Clock: smartcard_module_counter<8>_MC.Q)

\ From                               s     s     s     s
 \                                   m     m     m     m
  \                                  a     a     a     a
   \                                 r     r     r     r
    \                                t     t     t     t
     \                               c     c     c     c
      \                              a     a     a     a
       \                             r     r     r     r
        \                            d     d     d     d
         \                           _     _     _     _
          \                          m     m     m     m
           \                         o     o     o     o
            \                        d     d     d     d
             \                       u     u     u     u
              \                      l     l     l     l
               \                     e     e     e     e
                \                    _     _     _     _
                 \                   B     B     B     B
                  \                  i     i     i     i
                   \                 t     t     t     t
                    \                c     c     c     c
                     \               o     o     o     o
                      \              u     u     u     u
                       \             n     n     n     n
                        \            t     t     t     t
                         \           e     e     e     e
                          \          r     r     r     r
                           \         <     <     <     <
                            \        0     1     2     3
                             \       >     >     >     >
                              \      .     .     .     .
                               \     Q     Q     Q     Q
  To                            \------------------------

smartcard_module_Bitcounter<1>.D   3.2                  
smartcard_module_Bitcounter<2>.D   3.5   3.5   3.5   3.5
smartcard_module_Bitcounter<3>.D   3.5   3.5   3.5   3.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                   (Clock: smartcard_module_counter<6>_MC.Q)

\ From                               s     s     s     s
 \                                   m     m     m     m
  \                                  a     a     a     a
   \                                 r     r     r     r
    \                                t     t     t     t
     \                               c     c     c     c
      \                              a     a     a     a
       \                             r     r     r     r
        \                            d     d     d     d
         \                           _     _     _     _
          \                          m     m     m     m
           \                         o     o     o     o
            \                        d     d     d     d
             \                       u     u     u     u
              \                      l     l     l     l
               \                     e     e     e     e
                \                    _     _     _     _
                 \                   B     B     B     B
                  \                  i     i     i     i
                   \                 t     t     t     t
                    \                c     c     c     c
                     \               o     o     o     o
                      \              u     u     u     u
                       \             n     n     n     n
                        \            t     t     t     t
                         \           e     e     e     e
                          \          r     r     r     r
                           \         <     <     <     <
                            \        0     1     2     3
                             \       >     >     >     >
                              \      .     .     .     .
                               \     Q     Q     Q     Q
  To                            \------------------------

smartcard_module_Bitcounter<1>.D   3.2                  
smartcard_module_Bitcounter<2>.D   3.5   3.5   3.5   3.5
smartcard_module_Bitcounter<3>.D   3.5   3.5   3.5   3.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                   (Clock: smartcard_module_counter<7>_MC.Q)

\ From                               s     s     s     s
 \                                   m     m     m     m
  \                                  a     a     a     a
   \                                 r     r     r     r
    \                                t     t     t     t
     \                               c     c     c     c
      \                              a     a     a     a
       \                             r     r     r     r
        \                            d     d     d     d
         \                           _     _     _     _
          \                          m     m     m     m
           \                         o     o     o     o
            \                        d     d     d     d
             \                       u     u     u     u
              \                      l     l     l     l
               \                     e     e     e     e
                \                    _     _     _     _
                 \                   B     B     B     B
                  \                  i     i     i     i
                   \                 t     t     t     t
                    \                c     c     c     c
                     \               o     o     o     o
                      \              u     u     u     u
                       \             n     n     n     n
                        \            t     t     t     t
                         \           e     e     e     e
                          \          r     r     r     r
                           \         <     <     <     <
                            \        0     1     2     3
                             \       >     >     >     >
                              \      .     .     .     .
                               \     Q     Q     Q     Q
  To                            \------------------------

smartcard_module_Bitcounter<1>.D   3.2                  
smartcard_module_Bitcounter<2>.D   3.5   3.5   3.5   3.5
smartcard_module_Bitcounter<3>.D   3.5   3.5   3.5   3.5

--------------------------------------------------------------------------------
                          Clock to Setup (tCYC) (nsec)
                   (Clock: smartcard_module_counter<5>_MC.Q)

\ From                               s     s     s     s
 \                                   m     m     m     m
  \                                  a     a     a     a
   \                                 r     r     r     r
    \                                t     t     t     t
     \                               c     c     c     c
      \                              a     a     a     a
       \                             r     r     r     r
        \                            d     d     d     d
         \                           _     _     _     _
          \                          m     m     m     m