📄 top.tim
字号:
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<7>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<5>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<4>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<3>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<2>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<1>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_counter<0>.Q' path delays:
Clock to Setup (tCYC) : 3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D' (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'
Minimum Internal Clock Period: 3.5ns
Maximum Internal Clock Speed: 285.7Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.5ns
Maximum External Clock Speed (before divider): 285.7Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_Bitcounter<3>.Q' path delays:
Clock to Setup (tCYC) : 3.2ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bytecounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bytecounter<5>.D' (GCK)
Target FF drives output net 'smartcard_module_Bytecounter<5>'
Minimum Internal Clock Period: 3.2ns
Maximum Internal Clock Speed: 312.5Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.2ns
Maximum External Clock Speed (before divider): 312.5Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_Bitcounter<2>.Q' path delays:
Clock to Setup (tCYC) : 3.2ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bytecounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bytecounter<5>.D' (GCK)
Target FF drives output net 'smartcard_module_Bytecounter<5>'
Minimum Internal Clock Period: 3.2ns
Maximum Internal Clock Speed: 312.5Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.2ns
Maximum External Clock Speed (before divider): 312.5Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_Bitcounter<1>.Q' path delays:
Clock to Setup (tCYC) : 3.2ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bytecounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bytecounter<5>.D' (GCK)
Target FF drives output net 'smartcard_module_Bytecounter<5>'
Minimum Internal Clock Period: 3.2ns
Maximum Internal Clock Speed: 312.5Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.2ns
Maximum External Clock Speed (before divider): 312.5Mhz
(Limited by Cycle Time)
Clock net 'smartcard_module_Bitcounter<0>.Q' path delays:
Clock to Setup (tCYC) : 3.2ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bytecounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bytecounter<5>.D' (GCK)
Target FF drives output net 'smartcard_module_Bytecounter<5>'
Minimum Internal Clock Period: 3.2ns
Maximum Internal Clock Speed: 312.5Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 3.2ns
Maximum External Clock Speed (before divider): 312.5Mhz
(Limited by Cycle Time)
Clock net 'clk' path delays:
Clock Pad to Output Pad (tCO) : 21.5ns (8 macrocell levels)
Clock Pad 'clk' to Output Pad 'sram_addr<0>' (GCK)
Clock to Setup (tCYC) : 15.7ns (6 macrocell levels)
Clock to Q, net 'CurrentState_FFD3.Q' to DFF Setup(D) at 'lcd_module/DB_reg<3>.D' (GCK)
Target FF drives output net 'lcd_module/DB_reg<3>'
Setup to Clock at the Pad (tSU) : 4.7ns (1 macrocell levels)
Data signal 'sram_db<0>' to DFF D input Pin at 'CurrentState_FFD3.D'
Clock pad 'clk' (GCK)
Minimum Internal Clock Period: 15.7ns
Maximum Internal Clock Speed: 63.6Mhz
(Limited by Cycle Time)
Minimum External Clock Period: 15.7ns
Maximum External Clock Speed (before divider): 63.6Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Pad to Pad (tPD) (nsec)
\ From c
\ l
\ k
\
\
\
\
To \------
sc_clk 6.7
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From c
\ l
\ k
\
\
\
\
\
\
\
\
\
To \------
lcd_db<0> 10.5
lcd_db<1> 10.5
lcd_db<2> 10.5
lcd_db<3> 10.5
lcd_db<4> 10.5
lcd_db<5> 10.5
lcd_db<6> 10.5
lcd_db<7> 10.5
lcd_e 7.7
lcd_rs 7.7
sc_clk 8.0
sc_io 10.1
sc_reset 8.0
sram_addr<0> 21.5
sram_addr<1> 21.5
sram_addr<2> 21.5
sram_addr<3> 21.5
sram_addr<4> 21.5
sram_db<0> 16.9
sram_db<1> 16.9
sram_db<2> 16.9
sram_db<3> 16.9
sram_db<4> 16.9
sram_db<5> 16.9
sram_db<6> 16.9
sram_db<7> 16.9
sram_ioe 12.2
sram_iwe 16.9
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU or tSUF) (nsec)
\ From c
\ l
\ k
\
\
\
\
\
\
\
To \------
enable 1.9
sc_io 4.7
sram_db<0> 4.7
sram_db<1> 4.7
sram_db<2> 4.7
sram_db<3> 4.7
sram_db<4> 4.7
sram_db<5> 4.7
sram_db<6> 4.7
sram_db<7> 4.7
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: conver2ascii_module/counter<2>_MC.Q)
\ From c c c
\ o o o
\ n n n
\ v v v
\ e e e
\ r r r
\ 2 2 2
\ a a a
\ s s s
\ c c c
\ i i i
\ i i i
\ _ _ _
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -