top.tim

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

                           Performance Summary Report
                           --------------------------

Design:     top
Device:     XC2C256-5-TQ144
Speed File: Version 8.1 Advance Product Specification
Program:    Timing Report Generator:  version G.25a
Date:       Thu Nov 06 17:13:39 2003

Performance Summary:

Pad to Pad (tPD)                          :          6.7ns (1 macrocell levels)
Pad 'clk' to Pad 'sc_clk'                                         

Clock net 'conver2ascii_module/counter<2>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'conver2ascii_module/result_0_0.Q' to TFF Setup(D) at 'conver2ascii_module/result_0_1.D'        (GCK)
Target FF drives output net 'conver2ascii_module/result_0_1'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'conver2ascii_module/counter<3>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'conver2ascii_module/result_0_0.Q' to TFF Setup(D) at 'conver2ascii_module/result_0_1.D'        (GCK)
Target FF drives output net 'conver2ascii_module/result_0_1'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'conver2ascii_module/counter<1>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'conver2ascii_module/result_0_0.Q' to TFF Setup(D) at 'conver2ascii_module/result_0_1.D'        (GCK)
Target FF drives output net 'conver2ascii_module/result_0_1'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'conver2ascii_module/counter<0>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'conver2ascii_module/result_0_0.Q' to TFF Setup(D) at 'conver2ascii_module/result_0_1.D'        (GCK)
Target FF drives output net 'conver2ascii_module/result_0_1'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<0>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<2>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<1>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<4>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<7>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<3>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<6>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_Bytecounter<5>.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD5.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD4.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD6.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD3.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD2.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'CurrentState_FFD1.Q' path delays:

Clock to Setup (tCYC)                     :          3.2ns (1 macrocell levels)
Clock to Q, net 'Addr<0>.Q' to TFF Setup(D) at 'Addr<1>.D'                (GCK)
Target FF drives output net 'Addr<1>'

                      Minimum Internal Clock Period: 3.2ns
                     Maximum Internal Clock Speed: 312.5Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.2ns
            Maximum External Clock Speed (before divider): 312.5Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_counter<8>.Q' path delays:

Clock to Setup (tCYC)                     :          3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D'        (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'

                      Minimum Internal Clock Period: 3.5ns
                     Maximum Internal Clock Speed: 285.7Mhz
                            (Limited by Cycle Time)

                      Minimum External Clock Period: 3.5ns
            Maximum External Clock Speed (before divider): 285.7Mhz
                            (Limited by Cycle Time)

Clock net 'smartcard_module_counter<6>.Q' path delays:

Clock to Setup (tCYC)                     :          3.5ns (1 macrocell levels)
Clock to Q, net 'smartcard_module_Bitcounter<0>.Q' to TFF Setup(D) at 'smartcard_module_Bitcounter<2>.D'        (GCK)
Target FF drives output net 'smartcard_module_Bitcounter<2>'