lcd.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lcd is
    Port ( clk 		: in std_logic;
           reset 		: in std_logic;
			  DB			: in std_logic_vector(7 downto 0);
			  W			: in std_logic;
			  Ready	 	: inout std_logic;
			  line2		: in std_logic;
			  clear		: in std_logic;
           lcd_rs 	: out std_logic;
           lcd_rw 	: out std_logic;
           lcd_e 		: out std_logic;
           lcd_db 	: out std_logic_vector(7 downto 0));
end lcd;

architecture Behavioral of lcd is

constant N : natural := 30000;

component power_up is
    Port ( clk 				: in std_logic;
	 		  reset				: in std_logic;
			  counter_enable	: in std_logic;
           data 				: out std_logic_vector(7 downto 0);
			  count	 			: out std_logic_vector(15 downto 0);
           done 				: inout std_logic
			  );
end component;

-- signal W		: std_logic;

signal data 			: std_logic_vector(7 downto 0);
signal DB_reg 			: std_logic_vector(7 downto 0);
signal counter 		: std_logic_vector(15 downto 0);
signal init_done		: std_logic;

signal WriteDataState	: std_logic;
signal WriteC0State		: std_logic;
signal Write01State		: std_logic;

signal bitcounter 		: std_logic_vector(3 downto 0);
signal counter_enable	: std_logic;

--**************************************************************************
-- STATE MACHINE SIGNAL DECLARATION:
type StateType is (
							Init, 
							Standby, 
							WriteData,
							Write_done,
							WriteC0,
							Write01
							);

signal CurrentState, NextState : StateType;
--**************************************************************************

begin

	power_up_module: power_up
	port map (  clk 				=> clk,
	 		  		reset				=> reset,
					counter_enable => Ready,
           		data 				=> data,
			  		count	 			=> counter,
           		done 				=> init_done);


COMB: process(CurrentState, counter, W, init_done)
begin
	case CurrentState is


		when Init =>
			if(init_done = '1') then
				if(line2 = '1') then
					NextState <= WriteC0;		  
				else NextState <= Standby;
				end if;
			else NextState <= Init;
			end if;

		when Standby =>
			if(clear = '1') then
				NextState <= Write01;
			elsif(line2 = '1') then
				NextState <= WriteC0;			  
			elsif(W = '1') then		  
				NextState <= WriteData;
			else NextState <= Standby;
			end if;

		when WriteData =>
			if(counter >= N) then		  
				if(bitcounter = 15) then
					NextState <= WriteC0;
				else
					NextState <= Write_done;
				end if;
			else NextState <= WriteData;
			end if;

		when Write_done =>
				NextState <= Standby;

		when WriteC0 =>
			if(counter >= N) then		  
				NextState <= Write_done;
			else NextState <= WriteC0;
			end if;

		when Write01 =>
			if(counter >= N) then		  
				NextState <= Write_done;
			else NextState <= Write01;
			end if;


	end case;
end process COMB;

SEQ: process(reset, clk)
begin
	if(reset = '1') then
		CurrentState <= Init;
	elsif (clk'event and clk = '0') then
		CurrentState <= NextState;
	end if;
end process SEQ;


with CurrentState select
	Ready <= '1' when Standby,
			   '0' when Others;
				
with CurrentState select
	WriteDataState <= '1' when WriteData,
			   			'0' when Others; 

with CurrentState select
	WriteC0State <= '1' when WriteC0,
			   		 '0' when Others; 

with CurrentState select
	Write01State <= '1' when Write01,
			   		 '0' when Others; 


--**************************************************************************
--  4 bit counter
--**************************************************************************
counter_enable <= '1' when ((counter = 5) and (WriteDataState = '1')) else '0';
process(reset, clk, counter_enable)
begin
	if((reset = '1') or (line2 = '1')) then
		bitcounter <= (others=>'0');
	elsif (clk'event and clk = '0') then
		if(counter_enable = '1') then
			bitcounter <= bitcounter + 1;
		end if;
	end if;
end process;

-- DB latch
process(reset, clk, w)
begin
	if(reset = '1') then
		DB_reg <= (others=>'0');
	elsif (clk'event and clk = '0') then
		if((w = '1') and (ready = '1')) then
			DB_reg <= DB;
		end if;
	end if;
end process;
--
-- W <= '1';				
--**************************************************************
LCD_DB <= x"C0" when WriteC0State = '1' else
			 x"01" when Write01State = '1' else
			   DB_reg when init_done = '1' else
				data;
LCD_RS <= '1' when (WriteDataState = '1') else '0';
LCD_RW <= '0';	-- write only
LCD_E	 <= '1' when (counter = 5) else '0';
		 


end Behavioral;