📄 __projnav.log
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| Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 8-bit tristate buffer for signal <sram_db>. Found 9-bit comparator greater for signal <$n0086> created at line 641. Found 9-bit comparator less for signal <$n0087> created at line 641. Found 9-bit comparator greater for signal <$n0088> created at line 641. Found 9-bit comparator less for signal <$n0089> created at line 641. Found 5-bit up counter for signal <Addr>. Found 24-bit up counter for signal <counter>. Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 4 Comparator(s). inferred 8 Tristate(s).Unit <top> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 5# Registers : 3 10-bit register : 1 8-bit register : 1 1-bit register : 1# Counters : 10 16-bit up counter : 1 24-bit up counter : 1 8-bit down counter : 1 4-bit up counter : 4 9-bit up counter : 1 8-bit up counter : 1 5-bit up counter : 1# Multiplexers : 1 2-to-1 multiplexer : 1# Tristates : 4 1-bit tristate buffer : 3 8-bit tristate buffer : 1# Comparators : 12 17-bit comparator greatequal : 2 9-bit comparator greater : 4 9-bit comparator less : 4 5-bit comparator greatequal : 1 9-bit comparator greatequal : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Selecting encoding for FSM_4 ... Encoding for FSM_4 is Gray flip-flop = DSelecting encoding for FSM_3 ... Encoding for FSM_3 is Sequential flip-flop = DSelecting encoding for FSM_2 ... Encoding for FSM_2 is Sequential flip-flop = DSelecting encoding for FSM_1 ... Encoding for FSM_1 is Gray flip-flop = DSelecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = D=========================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1348 - Unit smartcard is merged (output interface has tristates)WARNING:Xst:637 - Naming conflict between signal Clk of unit Addr and signal Addr_Clk of unit top : renaming Addr_Clk to Addr_Clk1.WARNING:Xst:637 - Naming conflict between signal Clk of unit Bytecounter and signal Bytecounter_Clk of unit smartcard : renaming Bytecounter_Clk to Bytecounter_Clk1.WARNING:Xst:637 - Naming conflict between signal Clk of unit Bitcounter and signal Bitcounter_Clk of unit smartcard : renaming Bitcounter_Clk to Bitcounter_Clk1.Optimizing unit <top> ... implementation constraint: NOREDUCE : smartcard_module_card_io implementation constraint: KEEP : lcd_wOptimizing unit <conver2ascii> ...Optimizing unit <power_up> ...Optimizing unit <lcd> ...Completed process "Synthesize".
Started process "Translate".Release 6.1.02i - ngdbuild G.25aCopyright (c) 1995-2003 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc top.ucf -p xbr top.ngc top.ngd Reading NGO file "C:/work/app/smartcard/smartcard/top.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 37620 kilobytesWriting NGD file "top.ngd" ...Writing NGDBUILD log file "top.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.1.02i - CPLD Optimizer/Partitioner G.25aCopyright (c) 1995-2003 Xilinx, Inc. All rights reserved.Considering device XC2C256-5-TQ144.Re-checking device resources ......Synthesizing and Optimizing..................................................................................................o.......Fitting......................oDesign top has been optimized and fit into device XC2C256-5-TQ144.Completed process "Fit".
Started process "Generate Programming File".Release 6.1.02i - Programming File Generator G.25aCopyright (c) 1995-2003 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate Timing".Release 6.1.02i - Timing Report Generator G.25aCopyright (c) 1995-2003 Xilinx, Inc. All rights reserved.Path tracing ....................The number of paths traced: 3006................The number of paths traced: 6013.Generating performance summary ...Generating Pad-to-Pad delay section ...Generating Clock-to-Output-Pad delay section ...Generating Setup-To-Clock-At-Pad delay section ...Generating Register-To-Register delay section ... Cycle time table for clock conver2ascii_module/counter<2>_MC.Q ... Cycle time table for clock conver2ascii_module/counter<3>_MC.Q ... Cycle time table for clock conver2ascii_module/counter<1>_MC.Q ... Cycle time table for clock conver2ascii_module/counter<0>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<0>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<2>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<1>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<4>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<7>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<3>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<6>_MC.Q ... Cycle time table for clock smartcard_module_Bytecounter<5>_MC.Q ... Cycle time table for clock CurrentState_FFD5_MC.Q ... Cycle time table for clock CurrentState_FFD4_MC.Q ... Cycle time table for clock CurrentState_FFD6_MC.Q ... Cycle time table for clock CurrentState_FFD3_MC.Q ... Cycle time table for clock CurrentState_FFD2_MC.Q ... Cycle time table for clock CurrentState_FFD1_MC.Q ... Cycle time table for clock smartcard_module_counter<8>_MC.Q ... Cycle time table for clock smartcard_module_counter<6>_MC.Q ... Cycle time table for clock smartcard_module_counter<7>_MC.Q ... Cycle time table for clock smartcard_module_counter<5>_MC.Q ... Cycle time table for clock smartcard_module_counter<4>_MC.Q ... Cycle time table for clock smartcard_module_counter<3>_MC.Q ... Cycle time table for clock smartcard_module_counter<2>_MC.Q ... Cycle time table for clock smartcard_module_counter<1>_MC.Q ... Cycle time table for clock smartcard_module_counter<0>_MC.Q ... Cycle time table for clock smartcard_module_Bitcounter<3>_MC.Q ... Cycle time table for clock smartcard_module_Bitcounter<2>_MC.Q ... Cycle time table for clock smartcard_module_Bitcounter<1>_MC.Q ... Cycle time table for clock smartcard_module_Bitcounter<0>_MC.Q ... Cycle time table for clock clk ...top.tim has been created.Generating Stamp model files top.mod, top.data ...top.mod has been created.top.data has been created.Completed process "Generate Timing".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Archive". adding: automake.log (92 bytes security) (stored 0%) adding: binary2bcd.vhd (92 bytes security) (deflated 56%) adding: conver2ascii.vhd (92 bytes security) (deflated 68%) adding: lcd.vhd (92 bytes security) (deflated 74%) adding: power_up.vhd (92 bytes security) (deflated 73%) adding: smartcard.dhp (92 bytes security) (deflated 42%) adding: smartcard.npl (92 bytes security) (deflated 44%) adding: smartcard.vhd (92 bytes security) (deflated 81%) adding: tmperr.err (92 bytes security) (stored 0%) adding: top.bld (92 bytes security) (deflated 39%) adding: top.cmd_log (92 bytes security) (deflated 70%) adding: top.cxt (92 bytes security) (deflated 91%) adding: top.data (92 bytes security) (deflated 90%) adding: top.gyd (92 bytes security) (deflated 76%) adding: top.imp (92 bytes security) (stored 0%) adding: top.jed (92 bytes security) (deflated 90%) adding: top.log (92 bytes security) (stored 0%) adding: top.lso (92 bytes security) (stored 0%) adding: top.mfd (92 bytes security) (deflated 93%) adding: top.mod (92 bytes security) (deflated 81%) adding: top.ngc (92 bytes security) (deflated 79%) adding: top.ngd (92 bytes security) (deflated 82%) adding: top.ngr (92 bytes security) (deflated 64%) adding: top.pnx (92 bytes security) (deflated 81%) adding: top.prj (92 bytes security) (deflated 46%) adding: top.rpt (92 bytes security) (deflated 91%) adding: top.stx (92 bytes security) (stored 0%) adding: top.sym (92 bytes security) (deflated 78%) adding: top.syr (92 bytes security) (deflated 83%) adding: top.tim (92 bytes security) (deflated 97%) adding: top.ucf (92 bytes security) (deflated 76%) adding: top.ucf.untf (92 bytes security) (stored 0%) adding: top.vhd (92 bytes security) (deflated 80%) adding: top.vm6 (92 bytes security) (deflated 96%) adding: top.xml (92 bytes security) (deflated 93%) adding: top._hrpt (92 bytes security) (stored 0%) adding: top_build.xml (92 bytes security) (deflated 87%) adding: top_pad.csv (92 bytes security) (deflated 76%) adding: xst/ (92 bytes security) (stored 0%) adding: xst/work/ (92 bytes security) (stored 0%) adding: xst/work/hdllib.ref (92 bytes security) (deflated 77%) adding: xst/work/hdpdeps.ref (92 bytes security) (deflated 83%) adding: xst/work/sub00/ (92 bytes security) (stored 0%) adding: xst/work/sub00/vhpl00.vho (92 bytes security) (deflated 56%) adding: xst/work/sub00/vhpl01.vho (92 bytes security) (deflated 62%) adding: xst/work/sub00/vhpl02.vho (92 bytes security) (deflated 56%) adding: xst/work/sub00/vhpl03.vho (92 bytes security) (deflated 66%) adding: xst/work/sub00/vhpl04.vho (92 bytes security) (deflated 59%) adding: xst/work/sub00/vhpl05.vho (92 bytes security) (deflated 64%) adding: xst/work/sub00/vhpl06.vho (92 bytes security) (deflated 59%) adding: xst/work/sub00/vhpl07.vho (92 bytes security) (deflated 68%) adding: xst/work/sub00/vhpl08.vho (92 bytes security) (deflated 57%) adding: xst/work/sub00/vhpl09.vho (92 bytes security) (deflated 63%) adding: xst/work/sub00/vhpl10.vho (92 bytes security) (deflated 61%) adding: xst/work/sub00/vhpl11.vho (92 bytes security) (deflated 68%) adding: _impact.cmd (92 bytes security) (deflated 69%) adding: _impact.log (92 bytes security) (deflated 73%) adding: _ngo/ (92 bytes security) (stored 0%) adding: _ngo/netlist.lst (92 bytes security) (deflated 13%) adding: __projnav/ (92 bytes security) (stored 0%) adding: __projnav/p00i6000.kis (92 bytes security) (deflated 66%) adding: __projnav/p00i6001.kis (92 bytes security) (deflated 44%) adding: __projnav/p00i6002.kis (92 bytes security) (deflated 59%) adding: __projnav/p00i6003.kis (92 bytes security) (deflated 58%) adding: __projnav/p00i6004.kis (92 bytes security) (deflated 87%) adding: __projnav/p00l2000.kis (92 bytes security) (deflated 66%) adding: __projnav/p00l2001.kis (92 bytes security) (deflated 42%) adding: __projnav/p00l2002.kis (92 bytes security) (deflated 59%) adding: __projnav/p00l2003.kis (92 bytes security) (deflated 58%) adding: __projnav/p00l2004.kis (92 bytes security) (deflated 87%) adding: __projnav/runXst_tcl.rsp (92 bytes security) (deflated 14%) adding: __projnav/smartcard.gfl (92 bytes security) (deflated 76%) adding: __projnav/smartcard_flowplus.gfl (92 bytes security) (deflated 59%) adding: __projnav/top.xst (92 bytes security) (deflated 41%) adding: __projnav/top_edfTOngd_tcl.rsp (92 bytes security) (stored 0%) adding: __projnav/tozp_tcl.rsp (92 bytes security) (deflated 23%) adding: __projnav.log (92 bytes security) (deflated 89%)Completed process "Archive".
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