__projnav.log

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

Release 6.1.02i - ngdbuild G.25a
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc top.ucf -p xbr top.ngc top.ngd 

Reading NGO file "c:/work/app/smartcard/smartcard/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 37620 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Fit".

Release 6.1.02i - CPLD Optimizer/Partitioner G.25a
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Considering device XC2C256-5-TQ144.
Re-checking device resources ...
...
Synthesizing and Optimizing...
............................................................................................
...o
.......
Fitting...
.................................................................................................................
Cannot place 26 output(s) including 'conver2ascii_module/shifter<5>' to any
function block.
Fitter is running very low on: product terms, block inputs, I/O pins, macro
cells.
ERROR:Cpld:887 - Cannot fit the design into this device.
...o

ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 
Process "Fit" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".

Release 6.1.02i - ngdbuild G.25a
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc top.ucf -p xbr top.ngc top.ngd 

Reading NGO file "C:/work/app/smartcard/smartcard/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 37620 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Fit".

Release 6.1.02i - CPLD Optimizer/Partitioner G.25a
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Considering device XC2C256-5-TQ144.
Re-checking device resources ...
...
Synthesizing and Optimizing...
............................................................................................
...o
.......
Fitting...
.................................................................................................................
Cannot place 26 output(s) including 'conver2ascii_module/shifter<5>' to any
function block.
Fitter is running very low on: product terms, block inputs, I/O pins, macro
cells.
ERROR:Cpld:887 - Cannot fit the design into this device.
...o

ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 
Process "Fit" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/work/app/smartcard/smartcard/power_up.vhd in Library work.
Entity <power_up> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/work/app/smartcard/smartcard/lcd.vhd in Library work.
Entity <lcd> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/work/app/smartcard/smartcard/smartcard.vhd in Library work.
Entity <smartcard> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/work/app/smartcard/smartcard/conver2ascii.vhd in Library work.
Entity <conver2ascii> (Architecture <behavioral>) compiled.
Compiling vhdl file C:/work/app/smartcard/smartcard/top.vhd in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
    Set user-defined property "KEEP =  TRUE" for signal <lcd_w>.
WARNING:Xst:1541 - C:/work/app/smartcard/smartcard/top.vhd line 184: Different binding for component: <smartcard>. Port <data_out> does not match.
    Set user-defined property "NOREDUCE =  TRUE" for signal <card_io> in unit <smartcard>.
WARNING:Xst:819 - C:/work/app/smartcard/smartcard/top.vhd line 215: The following signals are missing in the process sensitivity list:
   char, ascii_done.
WARNING:Xst:819 - C:/work/app/smartcard/smartcard/top.vhd line 618: The following signals are missing in the process sensitivity list:
   clk.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <lcd> (Architecture <behavioral>).
WARNING:Xst:819 - C:/work/app/smartcard/smartcard/lcd.vhd line 78: The following signals are missing in the process sensitivity list:
   line2, clear, bitcounter<3>, bitcounter<2>, bitcounter<1>, bitcounter<0>.
WARNING:Xst:819 - C:/work/app/smartcard/smartcard/lcd.vhd line 162: The following signals are missing in the process sensitivity list:
   line2.
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <power_up> (Architecture <behavioral>).
Entity <power_up> analyzed. Unit <power_up> generated.

Analyzing Entity <smartcard> (Architecture <behavioral>).
    Set user-defined property "NOREDUCE =  TRUE" for signal <card_io> in unit <smartcard>.
WARNING:Xst:819 - C:/work/app/smartcard/smartcard/smartcard.vhd line 159: The following signals are missing in the process sensitivity list:
   Bitcounter_clk.
Entity <smartcard> analyzed. Unit <smartcard> generated.

Analyzing Entity <conver2ascii> (Architecture <behavioral>).
Entity <conver2ascii> analyzed. Unit <conver2ascii> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <power_up>.
    Related source file is C:/work/app/smartcard/smartcard/power_up.vhd.
WARNING:Xst:1778 - Inout <done> is assigned but never used.
    Found finite state machine <FSM_0> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 19                                             |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 17-bit comparator greatequal for signal <$n0019> created at line 50.
    Found 16-bit up counter for signal <counter>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <power_up> synthesized.


Synthesizing Unit <conver2ascii>.
    Related source file is C:/work/app/smartcard/smartcard/conver2ascii.vhd.
    Found finite state machine <FSM_1> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 5-bit comparator greatequal for signal <$n0006> created at line 104.
    Found 4-bit up counter for signal <counter>.
    Found 8-bit down counter for signal <dcount>.
    Found 4-bit up counter for signal <result>.
    Found 4 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred   1 Comparator(s).
Unit <conver2ascii> synthesized.


Synthesizing Unit <smartcard>.
    Related source file is C:/work/app/smartcard/smartcard/smartcard.vhd.
    Found finite state machine <FSM_2> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 13                                             |
    | Inputs             | 6                                              |
    | Outputs            | 6                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 1-bit tristate buffer for signal <card_vcc>.
    Found 1-bit tristate buffer for signal <card_vpp>.
    Found 1-bit tristate buffer for signal <card_io>.
    Found 9-bit comparator greatequal for signal <$n0025> created at line 326.
    Found 9-bit comparator greater for signal <$n0103> created at line 321.
    Found 9-bit comparator less for signal <$n0104> created at line 321.
    Found 9-bit comparator greater for signal <$n0105> created at line 321.
    Found 9-bit comparator less for signal <$n0106> created at line 321.
    Found 4-bit up counter for signal <Bitcounter>.
    Found 8-bit up counter for signal <Bytecounter>.
    Found 9-bit up counter for signal <counter>.
    Found 10-bit register for signal <data>.
    Found 1-bit register for signal <Enable_signal>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   3 Tristate(s).
Unit <smartcard> synthesized.


Synthesizing Unit <lcd>.
    Related source file is C:/work/app/smartcard/smartcard/lcd.vhd.
    Found finite state machine <FSM_3> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 15                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 17-bit comparator greatequal for signal <$n0013> created at line 103.
    Found 4-bit up counter for signal <bitcounter>.
    Found 8-bit register for signal <DB_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <lcd> synthesized.


Synthesizing Unit <top>.
    Related source file is C:/work/app/smartcard/smartcard/top.vhd.
WARNING:Xst:646 - Signal <sc_vpp> is assigned but never used.
WARNING:Xst:1780 - Signal <sram_w> is never used or assigned.
WARNING:Xst:646 - Signal <sc_vcc> is assigned but never used.
    Found finite state machine <FSM_4> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 43                                             |
    | Transitions        | 84                                             |
    | Inputs             | 8                                              |
    | Outputs            | 10                                             |
    | Reset type         | asynchronous                                   |