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SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file c:/work/app/smartcard/smartcard/binary2bcd.vhd in Library work.
Entity <binary2bcd> (Architecture <Behavioral>) compiled.
Compiling vhdl file c:/work/app/smartcard/smartcard/power_up.vhd in Library work.
Entity <power_up> (Architecture <Behavioral>) compiled.
Compiling vhdl file c:/work/app/smartcard/smartcard/lcd.vhd in Library work.
Entity <lcd> (Architecture <Behavioral>) compiled.
Compiling vhdl file c:/work/app/smartcard/smartcard/smartcard.vhd in Library work.
Entity <smartcard> (Architecture <Behavioral>) compiled.
Compiling vhdl file c:/work/app/smartcard/smartcard/conver2ascii.vhd in Library work.
Entity <conver2ascii> (Architecture <Behavioral>) compiled.
Compiling vhdl file c:/work/app/smartcard/smartcard/top.vhd in Library work.
Entity <top> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <Behavioral>).
    Set user-defined property "KEEP =  TRUE" for signal <lcd_w>.
WARNING:Xst:1541 - c:/work/app/smartcard/smartcard/top.vhd line 181: Different binding for component: <smartcard>. Port <data_out> does not match.
    Set user-defined property "NOREDUCE =  TRUE" for signal <card_io> in unit <smartcard>.
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/top.vhd line 212: The following signals are missing in the process sensitivity list:
   char, ascii_done.
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/top.vhd line 615: The following signals are missing in the process sensitivity list:
   clk.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <lcd> (Architecture <behavioral>).
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/lcd.vhd line 78: The following signals are missing in the process sensitivity list:
   line2, clear, bitcounter<3>, bitcounter<2>, bitcounter<1>, bitcounter<0>.
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/lcd.vhd line 162: The following signals are missing in the process sensitivity list:
   line2.
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <power_up> (Architecture <behavioral>).
Entity <power_up> analyzed. Unit <power_up> generated.

Analyzing Entity <smartcard> (Architecture <behavioral>).
    Set user-defined property "NOREDUCE =  TRUE" for signal <card_io> in unit <smartcard>.
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/smartcard.vhd line 157: The following signals are missing in the process sensitivity list:
   Bitcounter_clk.
Entity <smartcard> analyzed. Unit <smartcard> generated.

Analyzing Entity <conver2ascii> (Architecture <behavioral>).
    Set user-defined property "KEEP =  TRUE" for signal <shift_enable>.
WARNING:Xst:819 - c:/work/app/smartcard/smartcard/conver2ascii.vhd line 129: The following signals are missing in the process sensitivity list:
   reset.
Entity <conver2ascii> analyzed. Unit <conver2ascii> generated.

Analyzing Entity <binary2bcd> (Architecture <behavioral>).
Entity <binary2bcd> analyzed. Unit <binary2bcd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <binary2bcd>.
    Related source file is c:/work/app/smartcard/smartcard/binary2bcd.vhd.
    Found 5-bit comparator greatequal for signal <$n0004> created at line 31.
    Found 1-bit xor2 for signal <$n0005> created at line 34.
    Found 4-bit register for signal <q>.
    Found 1 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Comparator(s).
	inferred   1 Xor(s).
Unit <binary2bcd> synthesized.


Synthesizing Unit <power_up>.
    Related source file is c:/work/app/smartcard/smartcard/power_up.vhd.
WARNING:Xst:1778 - Inout <done> is assigned but never used.
    Found finite state machine <FSM_0> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 19                                             |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 17-bit comparator greatequal for signal <$n0019> created at line 50.
    Found 16-bit up counter for signal <counter>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <power_up> synthesized.


Synthesizing Unit <conver2ascii>.
    Related source file is c:/work/app/smartcard/smartcard/conver2ascii.vhd.
WARNING:Xst:646 - Signal <c1> is assigned but never used.
    Found finite state machine <FSM_1> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 3                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <dout>.
    Found 4-bit up counter for signal <counter>.
    Found 8-bit register for signal <shifter>.
    Found 16 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
Unit <conver2ascii> synthesized.


Synthesizing Unit <smartcard>.
    Related source file is c:/work/app/smartcard/smartcard/smartcard.vhd.
    Found finite state machine <FSM_2> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 13                                             |
    | Inputs             | 6                                              |
    | Outputs            | 6                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 1-bit tristate buffer for signal <card_vcc>.
    Found 1-bit tristate buffer for signal <card_vpp>.
    Found 1-bit tristate buffer for signal <card_io>.
    Found 9-bit comparator greatequal for signal <$n0025> created at line 324.
    Found 9-bit comparator greater for signal <$n0103> created at line 319.
    Found 9-bit comparator less for signal <$n0104> created at line 319.
    Found 9-bit comparator greater for signal <$n0105> created at line 319.
    Found 9-bit comparator less for signal <$n0106> created at line 319.
    Found 4-bit up counter for signal <Bitcounter>.
    Found 8-bit up counter for signal <Bytecounter>.
    Found 9-bit up counter for signal <counter>.
    Found 10-bit register for signal <data>.
    Found 1-bit register for signal <Enable_signal>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   3 Tristate(s).
Unit <smartcard> synthesized.


Synthesizing Unit <lcd>.
    Related source file is c:/work/app/smartcard/smartcard/lcd.vhd.
    Found finite state machine <FSM_3> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 15                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 17-bit comparator greatequal for signal <$n0013> created at line 103.
    Found 4-bit up counter for signal <bitcounter>.
    Found 8-bit register for signal <DB_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <lcd> synthesized.


Synthesizing Unit <top>.
    Related source file is c:/work/app/smartcard/smartcard/top.vhd.
WARNING:Xst:646 - Signal <sc_vpp> is assigned but never used.
WARNING:Xst:1780 - Signal <sram_w> is never used or assigned.
WARNING:Xst:646 - Signal <sc_vcc> is assigned but never used.
    Found finite state machine <FSM_4> for signal <CurrentState>.
    -----------------------------------------------------------------------
    | States             | 43                                             |
    | Transitions        | 84                                             |
    | Inputs             | 8                                              |
    | Outputs            | 10                                             |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Found 8-bit tristate buffer for signal <sram_db>.
    Found 9-bit comparator greater for signal <$n0086> created at line 626.
    Found 9-bit comparator less for signal <$n0087> created at line 626.
    Found 9-bit comparator greater for signal <$n0088> created at line 626.
    Found 9-bit comparator less for signal <$n0089> created at line 626.
    Found 5-bit up counter for signal <Addr>.
    Found 24-bit up counter for signal <counter>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred   4 Comparator(s).
	inferred   8 Tristate(s).
Unit <top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 5
# Registers                        : 7
  4-bit register                   : 2
  10-bit register                  : 1
  8-bit register                   : 3
  1-bit register                   : 1
# Counters                         : 8
  16-bit up counter                : 1
  4-bit up counter                 : 3
  9-bit up counter                 : 1
  8-bit up counter                 : 1
  5-bit up counter                 : 1
  24-bit up counter                : 1
# Multiplexers                     : 8
  2-to-1 multiplexer               : 8
# Tristates                        : 4
  1-bit tristate buffer            : 3
  8-bit tristate buffer            : 1
# Comparators                      : 13
  5-bit comparator greatequal      : 2
  9-bit comparator greater         : 4
  9-bit comparator less            : 4
  17-bit comparator greatequal     : 2
  9-bit comparator greatequal      : 1
# Xors                             : 2
  1-bit xor2                       : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_4 ...
	Encoding for FSM_4 is Gray flip-flop = D
Selecting encoding for FSM_3 ...
	Encoding for FSM_3 is Sequential flip-flop = D
Selecting encoding for FSM_2 ...
	Encoding for FSM_2 is Sequential flip-flop = D
Selecting encoding for FSM_1 ...
	Encoding for FSM_1 is Gray flip-flop = D
Selecting encoding for FSM_0 ...
	Encoding for FSM_0 is Sequential flip-flop = D

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1348 - Unit smartcard is merged (output interface has tristates)
WARNING:Xst:637 - Naming conflict between signal Clk of unit Addr and signal Addr_Clk of unit top : renaming Addr_Clk to Addr_Clk1.
WARNING:Xst:637 - Naming conflict between signal Clk of unit Bytecounter and signal Bytecounter_Clk of unit smartcard : renaming Bytecounter_Clk to Bytecounter_Clk1.
WARNING:Xst:637 - Naming conflict between signal Clk of unit Bitcounter and signal Bitcounter_Clk of unit smartcard : renaming Bitcounter_Clk to Bitcounter_Clk1.
WARNING:Xst:1710 - FF/Latch  <dout_7> (without init value) is constant in block <conver2ascii>.
WARNING:Xst:1710 - FF/Latch  <dout_6> (without init value) is constant in block <conver2ascii>.

Optimizing unit <top> ...
  implementation constraint: NOREDUCE	 : smartcard_module_card_io
  implementation constraint: KEEP	 : lcd_w

Optimizing unit <binary2bcd> ...

Optimizing unit <conver2ascii> ...
  implementation constraint: KEEP	 : shift_enable
WARNING:Xst:1426 - The value init of the FF/Latch dout_5 hinder the constant cleaning in the block conver2ascii.
   You should achieve better results by setting this init to 1.
WARNING:Xst:1426 - The value init of the FF/Latch dout_4 hinder the constant cleaning in the block conver2ascii.
   You should achieve better results by setting this init to 1.
Register dout_5 equivalent to dout_4 has been removed

Optimizing unit <power_up> ...

Optimizing unit <lcd> ...
Completed process "Synthesize".



Started process "Translate".