binary2bcd.vhd

来自「SD卡读写的VHDL VHDL Source Files in Smartca」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity binary2bcd is
    Port ( clk : in std_logic;
           init : in std_logic;
           di : in std_logic;
           do : out std_logic;
           qo : out std_logic_vector(3 downto 0));
end binary2bcd;

architecture Behavioral of binary2bcd is

signal q: std_logic_vector(3 downto 0);
signal m: std_logic_vector(3 downto 1);
signal n: std_logic_vector(3 downto 1);
signal g5: std_logic;

begin

qo <= q;
do <= g5;

g5 <= '1' when (q >= 5 and init = '1') else '0';

m(3) <= (q(3) and q(0)) when (g5 = '1') else q(2);
m(2) <= (not (q(1) xor q(0))) when (g5 = '1') else q(1);
m(1) <= (not q(0)) when (g5 = '1') else q(0);

n(3) <= m(3) and  init;
n(2) <= m(2) and  init;
n(1) <= m(1) and  init;

process (clk)
begin
	if(clk'event and clk = '1') then
		q <= n & di;
	end if;
end process;		

end Behavioral;