top.vhd

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity top is
    Port ( clk 		: in std_logic;
           reset 		: in std_logic;
           --
			  dce 		: out std_logic;
           lcd_rs 	: out std_logic;
           lcd_rw 	: out std_logic;
           lcd_e 		: out std_logic;
           lcd_db 	: out std_logic_vector(7 downto 0);
			  --led		 	: out std_logic_vector(7 downto 0);
			  --
			  sram_addr : out std_logic_vector(12 downto 0);
			  sram_db 	: inout std_logic_vector(7 downto 0);
			  sram_ioe	: out std_logic;
			  sram_iwe	: out std_logic;
			  sram_ice	: out std_logic;
			  --
			  enable 	: in std_logic;
			  sc_clk 	: out std_logic;
           sc_reset 	: out std_logic;
           sc_io 		: inout std_logic);
			  attribute KEEP : string;
end top;

architecture Behavioral of top is

component smartcard is
    Port ( reset_button 	: in std_logic;
           card_enable 		: in std_logic;
           clk 				: in std_logic;
           card_vpp 			: out std_logic;
           card_vcc 			: out std_logic;
           card_clk 			: out std_logic;
           card_rst	 		: out std_logic;
           card_io 			: inout std_logic;
			  data_ready		: out std_logic;
			  done				: out std_logic;
           data_out			: out std_logic_vector(0 to 7));
end component;

component lcd is
    Port ( clk 		: in std_logic;
           reset 		: in std_logic;
			  DB			: in std_logic_vector(7 downto 0);
			  W			: in std_logic;
			  Ready	 	: inout std_logic;
			  line2		: in std_logic;
			  clear		: in std_logic;
           lcd_rs 	: out std_logic;
           lcd_rw 	: out std_logic;
           lcd_e 		: out std_logic;
           lcd_db 	: out std_logic_vector(7 downto 0));
end component;


component conver2ascii is
    Port ( clk : in std_logic;
           reset : in std_logic;
           din : in std_logic_vector(7 downto 0);
			  ref : in std_logic;	-- 0 - 1s, 1 - 10s
			  done : out std_logic;
           dout : out std_logic_vector(7 downto 0));
end component;

--signal add_8 : std_logic;
--signal ledclk : std_logic;
signal ireset : std_logic;
signal DA 	: std_logic_vector(7 downto 0);
signal DB 	: std_logic_vector(7 downto 0);
signal char	: std_logic;
--signal num	: std_logic;
signal counter 	: std_logic_vector(23 downto 0);
signal counter_enable	: std_logic;
signal nextscreen	: std_logic;
signal CharBus 	: std_logic_vector(7 downto 0);
signal AddrBus : std_logic_vector(12 downto 0);

--attribute KEEP of DB : signal is "TRUE";

signal Addr : std_logic_vector(4 downto 0);
signal sram_w : std_logic;
signal addr_clk	: std_logic;
signal sram_reset : std_logic;


signal lcd_ready	: std_logic;
signal lcd_nextc	: std_logic;
signal lcd_w	: std_logic;
signal lcd_line2 : std_logic;

attribute KEEP of lcd_w : signal is "TRUE";

signal sc_vpp	: std_logic;
signal sc_vcc	: std_logic;
signal sc_data_ready	: std_logic;
signal sc_done	: std_logic;
signal sc_done_bar	: std_logic;

signal ascii_enable : std_logic;
signal ascii_ref : std_logic;
signal ascii_done : std_logic;
signal ascii_db : std_logic_vector(7 downto 0);

--**************************************************************************
-- STATE MACHINE SIGNAL DECLARATION:
type StateType is (
							Idle, 
							Standby,
							WriteCommand,
							WriteData,
							Nextc,
							gotonextline,
							getsex,
							CheckSex,
							Char_F,
							Char_E,
							Char_M,
							Char_A,
							Char_L,
							Char_E2,
							delay_loop,
							clearscreen,
							getstatus,
							CheckStatus,
							Char_1S,
							Char_1I,
							Char_1N,
							Char_1G,
							Char_1L,
							Char_1E,
							Char_2M,
							Char_2A,
							Char_2R,
							Char_3R,
							Char_2I,
							Char_2E,
							Char_2D,
							gotonextline1,
							Char_3A,
							Char_3G,
							Char_3E,
							Char_space,
							getage,
							Get_Char_10s,
							Char_10s,
							Char_10s_done,
							Get_Char_ones,
							Char_ones,
							stop   
							);

signal CurrentState, NextState : StateType;
--**************************************************************************


begin


-- lcd display interface
lcd_module: lcd
    Port map(  clk 		=> clk,
           		reset 	=> sc_done_bar, --reset,
			  		DB			=> CharBus,
			  		W			=> lcd_w,
			  		Ready	 	=> lcd_ready,
					line2		=> lcd_line2,
					clear		=> nextscreen,
           		lcd_rs 	=> lcd_rs,
           		lcd_rw 	=> lcd_rw,
           		lcd_e 	=> lcd_e,
           		lcd_db 	=> lcd_db);

-- smartcard interface
smartcard_module: smartcard
    Port map(  reset_button 	=> ireset,
           		card_enable 	=> enable,
			  		clk				=> clk,
			  		card_vpp			=> sc_vpp,
			  		card_vcc	 		=> sc_vcc,
           		card_clk 		=> sc_clk,
           		card_rst 		=> sc_reset,
           		card_io 			=> sc_io,
					data_ready		=> sc_data_ready,
					done				=> sc_done,
           		data_out 		=> DA);

-- number decoder interface
conver2ascii_module: conver2ascii
    Port map(  clk 	=> clk,
           		reset	=> ascii_enable,
			  		din	=> DB,
			  		ref	=> ascii_ref,
			  		done	=> ascii_done,
           		dout	=> ascii_db);

-- SRAM interface
sram_ice <= '0';
sram_addr <= addrBus;
sram_db <= DA when (sc_done = '0') else (others => 'Z');
DB <=	sram_db;
sram_iwe <= not sc_data_ready;
sram_ioe <= not sc_done;


COMB: process(CurrentState, sc_done, lcd_ready, addr, counter, DB)
begin
	case CurrentState is


		when Idle =>						  -- the state machine will start when
			if(sc_done = '1') then		  -- smart card data are read and saved
				NextState <= Standby;	  -- to sram
			else NextState <= Idle;
			end if;

		when Standby =>
			if(lcd_ready = '1') then		  
				NextState <= WriteCommand;
			else NextState <= Standby;
			end if;

		when WriteCommand =>
			NextState <= WriteData;

		when WriteData =>
			if(lcd_ready = '1') then		  
				NextState <= Nextc;
			else NextState <= WriteData;
			end if;

		when Nextc =>
			if((addr = 15) or (char = '0')) then --limited to 15 characters
			--if((addr >= 15)) then		
				NextState <= gotonextline;
			else NextState <= WriteCommand;
			end if;

		when gotonextline =>
			if((lcd_ready = '1')) then		  
				NextState <= getsex;
			else NextState <= gotonextline;
			end if;


		when getsex =>
			if(lcd_ready = '1') then		  
				NextState <= CheckSex;
			else NextState <= getsex;
			end if;

		when CheckSex =>
			if (DB = 1) then		  
				NextState <= char_M;
			else if (DB = 2) then
					NextState <= char_F;
				else NextState <= stop;
				end if;
			end if;

		when char_F =>
			if((lcd_ready = '1')) then		  
				NextState <= char_E;
			else NextState <= char_F;
			end if;

		when char_E =>
			if((lcd_ready = '1')) then		  
				NextState <= char_M;
			else NextState <= char_E;
			end if;

		when char_M =>
			if((lcd_ready = '1')) then		  
				NextState <= char_A;
			else NextState <= char_M;
			end if;

		when char_A =>
			if((lcd_ready = '1')) then		  
				NextState <= char_L;
			else NextState <= char_A;
			end if;

		when char_L =>
			if((lcd_ready = '1')) then		  
				NextState <= char_E2;
			else NextState <= char_L;
			end if;

		when char_E2 =>
			if((lcd_ready = '1')) then		  
				NextState <= delay_loop;
			else NextState <= char_E2;
			end if;

		when delay_loop =>
			if (counter = 2097151) then	-- ~2 sec delay
				NextState <= clearscreen;
			else
				NextState <= delay_loop;
			end if;

		when clearscreen =>
			NextState <= getstatus;

		when getstatus =>
			if(lcd_ready = '1') then		  
				NextState <= CheckStatus;
			else NextState <= getstatus;
			end if;

		when CheckStatus =>
			if (DB = 1) then		  
				NextState <= char_1S;