top.mod

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

MODEL
MODEL_VERSION "v1998.8";
DESIGN "top";

/* port names and type */
INPUT S:PIN38 = clk;
INPUT S:PIN43 = enable;
INPUT S:PIN32 = reset;
OUTPUT S:PIN23 = dce;
TRIOUT S:PIN103 = sram_db<0>;
TRIOUT S:PIN126 = sram_db<7>;
TRIOUT S:PIN128 = sram_db<6>;
TRIOUT S:PIN129 = sram_db<5>;
TRIOUT S:PIN130 = sram_db<4>;
TRIOUT S:PIN131 = sram_db<3>;
TRIOUT S:PIN101 = sram_db<2>;
TRIOUT S:PIN102 = sram_db<1>;
TRIOUT S:PIN41 = sc_io;
OUTPUT S:PIN4 = lcd_db<0>;
OUTPUT S:PIN3 = lcd_db<1>;
OUTPUT S:PIN2 = lcd_db<2>;
OUTPUT S:PIN30 = lcd_db<3>;
OUTPUT S:PIN28 = lcd_db<4>;
OUTPUT S:PIN26 = lcd_db<5>;
OUTPUT S:PIN25 = lcd_db<6>;
OUTPUT S:PIN24 = lcd_db<7>;
OUTPUT S:PIN34 = lcd_e;
OUTPUT S:PIN40 = lcd_rs;
OUTPUT S:PIN35 = lcd_rw;
OUTPUT S:PIN39 = sc_clk;
OUTPUT S:PIN42 = sc_reset;
OUTPUT S:PIN104 = sram_addr<0>;
OUTPUT S:PIN124 = sram_addr<10>;
OUTPUT S:PIN120 = sram_addr<11>;
OUTPUT S:PIN114 = sram_addr<12>;
OUTPUT S:PIN105 = sram_addr<1>;
OUTPUT S:PIN106 = sram_addr<2>;
OUTPUT S:PIN107 = sram_addr<3>;
OUTPUT S:PIN110 = sram_addr<4>;
OUTPUT S:PIN111 = sram_addr<5>;
OUTPUT S:PIN112 = sram_addr<6>;
OUTPUT S:PIN113 = sram_addr<7>;
OUTPUT S:PIN118 = sram_addr<8>;
OUTPUT S:PIN119 = sram_addr<9>;
OUTPUT S:PIN125 = sram_ice;
OUTPUT S:PIN121 = sram_ioe;
OUTPUT S:PIN116 = sram_iwe;

/* timing arc definitions */
clk_sc_clk_delay: DELAY clk sc_clk;
clk_sram_db<0>_delay: DELAY (ENABLE_HIGH) clk sram_db<0>;
clk_sram_db<7>_delay: DELAY (ENABLE_HIGH) clk sram_db<7>;
clk_sram_db<6>_delay: DELAY (ENABLE_HIGH) clk sram_db<6>;
clk_sram_db<5>_delay: DELAY (ENABLE_HIGH) clk sram_db<5>;
clk_sram_db<4>_delay: DELAY (ENABLE_HIGH) clk sram_db<4>;
clk_sram_db<3>_delay: DELAY (ENABLE_HIGH) clk sram_db<3>;
clk_sram_db<2>_delay: DELAY (ENABLE_HIGH) clk sram_db<2>;
clk_sram_db<1>_delay: DELAY (ENABLE_HIGH) clk sram_db<1>;
clk_sc_io_delay: DELAY (ENABLE_HIGH) clk sc_io;
clk_lcd_db<0>_delay: DELAY clk lcd_db<0>;
clk_lcd_db<1>_delay: DELAY clk lcd_db<1>;
clk_lcd_db<2>_delay: DELAY clk lcd_db<2>;
clk_lcd_db<3>_delay: DELAY clk lcd_db<3>;
clk_lcd_db<4>_delay: DELAY clk lcd_db<4>;
clk_lcd_db<5>_delay: DELAY clk lcd_db<5>;
clk_lcd_db<6>_delay: DELAY clk lcd_db<6>;
clk_lcd_db<7>_delay: DELAY clk lcd_db<7>;
clk_lcd_e_delay: DELAY clk lcd_e;
clk_lcd_rs_delay: DELAY clk lcd_rs;
clk_sc_clk_delay: DELAY clk sc_clk;
clk_sc_reset_delay: DELAY clk sc_reset;
clk_sram_addr<0>_delay: DELAY clk sram_addr<0>;
clk_sram_addr<1>_delay: DELAY clk sram_addr<1>;
clk_sram_addr<2>_delay: DELAY clk sram_addr<2>;
clk_sram_addr<3>_delay: DELAY clk sram_addr<3>;
clk_sram_addr<4>_delay: DELAY clk sram_addr<4>;
clk_sram_ioe_delay: DELAY clk sram_ioe;
clk_sram_iwe_delay: DELAY clk sram_iwe;

/* timing check arc definitions */
enable_clk_setup: SETUP(POSEDGE) enable clk;
sc_io_clk_setup: SETUP(POSEDGE) sc_io clk;
sram_db<0>_clk_setup: SETUP(POSEDGE) sram_db<0> clk;
sram_db<1>_clk_setup: SETUP(POSEDGE) sram_db<1> clk;
sram_db<2>_clk_setup: SETUP(POSEDGE) sram_db<2> clk;
sram_db<3>_clk_setup: SETUP(POSEDGE) sram_db<3> clk;
sram_db<4>_clk_setup: SETUP(POSEDGE) sram_db<4> clk;
sram_db<5>_clk_setup: SETUP(POSEDGE) sram_db<5> clk;
sram_db<6>_clk_setup: SETUP(POSEDGE) sram_db<6> clk;
sram_db<7>_clk_setup: SETUP(POSEDGE) sram_db<7> clk;
enable_clk_hold: HOLD(POSEDGE) enable clk;
sc_io_clk_hold: HOLD(POSEDGE) sc_io clk;
sram_db<0>_clk_hold: HOLD(POSEDGE) sram_db<0> clk;
sram_db<1>_clk_hold: HOLD(POSEDGE) sram_db<1> clk;
sram_db<2>_clk_hold: HOLD(POSEDGE) sram_db<2> clk;
sram_db<3>_clk_hold: HOLD(POSEDGE) sram_db<3> clk;
sram_db<4>_clk_hold: HOLD(POSEDGE) sram_db<4> clk;
sram_db<5>_clk_hold: HOLD(POSEDGE) sram_db<5> clk;
sram_db<6>_clk_hold: HOLD(POSEDGE) sram_db<6> clk;
sram_db<7>_clk_hold: HOLD(POSEDGE) sram_db<7> clk;

ENDMODEL