top.pnx

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (LVTTL|SSTL3_I|LVCMOS33|LVCMOS25|SSTL2_I|LVCMOS18|LVCMOS15|HSTL_I|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW"
  dir    (BIDIR|bidir|INPUT|input|OUTPUT|output) "BIDIR">
]>
<ibis><part pkg="TQ144" spg="-5" arch="xbr" device="XC2C256"/><pin nm="clk" no="38" dir="input" iostd="LVCMOS33"/><pin nm="enable" no="43" dir="input" iostd="LVCMOS33"/><pin nm="reset" no="32" dir="input" iostd="LVCMOS33"/><pin nm="dce" no="23" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;0&gt;" no="4" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;1&gt;" no="3" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;2&gt;" no="2" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;3&gt;" no="30" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;4&gt;" no="28" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;5&gt;" no="26" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;6&gt;" no="25" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_db&lt;7&gt;" no="24" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_e" no="34" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_rs" no="40" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="lcd_rw" no="35" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sc_clk" no="39" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sc_reset" no="42" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;0&gt;" no="104" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;10&gt;" no="124" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;11&gt;" no="120" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;12&gt;" no="114" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;1&gt;" no="105" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;2&gt;" no="106" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;3&gt;" no="107" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;4&gt;" no="110" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;5&gt;" no="111" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;6&gt;" no="112" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;7&gt;" no="113" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;8&gt;" no="118" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_addr&lt;9&gt;" no="119" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_ice" no="125" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_ioe" no="121" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sram_iwe" no="116" sr="fast" dir="output" iostd="LVCMOS33"/><pin nm="sc_io" no="41" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;0&gt;" no="103" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;1&gt;" no="102" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;2&gt;" no="101" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;3&gt;" no="131" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;4&gt;" no="130" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;5&gt;" no="129" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;6&gt;" no="128" sr="fast" dir="bidir" iostd="LVCMOS33"/><pin nm="sram_db&lt;7&gt;" no="126" sr="fast" dir="bidir" iostd="LVCMOS33"/></ibis>