conver2ascii.vhd

SD卡读写的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2asci

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity conver2ascii is
    Port ( clk : in std_logic;
           reset : in std_logic;
           din : in std_logic_vector(7 downto 0);
			  ref : in std_logic;	-- 0 - 1s, 1 - 10s
			  done : out std_logic;
           dout : out std_logic_vector(7 downto 0));
end conver2ascii;

architecture Behavioral of conver2ascii is

signal counter : std_logic_vector(3 downto 0);
signal result : std_logic_vector(3 downto 0);
signal data : std_logic_vector(3 downto 0);
signal rclk : std_logic;
signal le : std_logic;
signal zero : std_logic;
signal stopstate : std_logic;
signal dcount : std_logic_vector(7 downto 0);

--**************************************************************************
-- STATE MACHINE SIGNAL DECLARATION:
type StateType is (
							Start, 
							GetData,
							StartCount,
							stop   
							);

signal CurrentState, NextState : StateType;
--**************************************************************************

begin

COMB: process(CurrentState, dcount)
begin
	case CurrentState is

		when start =>
			NextState <= GetData;

		when GetData =>
			NextState <= StartCount;

		when StartCount =>
			if(dcount = 0) then
				NextState <= stop;
			else NextState <= StartCount;
			end if;

		when stop =>
			NextState <= stop;

	end case;
end process COMB;

SEQ: process(reset, clk)
begin
	if(reset = '0') then
		CurrentState <= Start;
	elsif (clk'event and clk = '1') then
		CurrentState <= NextState;
	end if;
end process SEQ;

with CurrentState select
	le <= '1' when GetData,
			'0' when Others;

with CurrentState select
	stopstate <= '1' when Stop,
			       '0' when Others;


-- latch data and count down
process(clk, le)
begin
	if (clk'event and clk = '1') then
		if(le = '1') then
			dcount <= din;
		else
			dcount <= dcount - 1;
		end if;
	end if;
end process;

-- terminal counter
process(clk, le, counter)
begin
	if(le = '1') then
		counter <= (others => '0');
	elsif (clk'event and clk = '1') then
		if(zero = '1') then
			counter <= counter;
		elsif (counter >= 9) then
				counter <= (others => '0');
		else counter <= counter + 1;
		end if;
	end if;
end process;

-- result counter
rclk <= '0' when (counter = 9) else '1';
process(rclk, le)
begin
	if(le = '1') then
		result <= (others => '0');
	elsif (rclk'event and rclk = '1') then
		if(zero = '1') then
			result <= result;
		else result <= result + 1;
		end if;
	end if;
end process;

zero <= '1' when ((dcount = 0) or (stopstate = '1')) else '0';
done <= stopstate;
data <= result when (ref = '1') else counter;
dout <= "0011" & data;

end Behavioral;