inita.c

visual dsp++环境下

//***********************************************************************
//      Init routine for the TigerSHARC EZ-Kit DSP A
//      Audio Pass Through example in C
//      Inita.c
//***********************************************************************
        
//************************* Includes ************************************
#include <sysreg.h>
#include <builtins.h>
#include <defTS201.h>
#include <signal.h>
#include "TSEZKitDef.h"
#include "PassThroughDef.h"

//************************* Externs *************************************
extern TCBChain XmitDMALSourceTCB, XmitDMALDestinTCB, XmitDMARSourceTCB, XmitDMARDestinTCB,
                RcveDMALSourceTCB, RcveDMALDestinTCB, RcveDMARSourceTCB, RcveDMARDestinTCB;


//********************* Function declares *******************************
void audio_int();
void SetTCB0(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
             long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin);

//***********************************************************************
void inita( void )
{
    volatile int temp;

//------------------------- Init SYSCON and SDRCON ----------------------
                                     
    __builtin_sysreg_write(__SYSCON, SYSCON_MP_WID64 |       
                                     SYSCON_MEM_WID64 |
	                                 SYSCON_MSH_PIPE2 |
                                     SYSCON_MSH_WT0 |  
                                     SYSCON_MSH_IDLE | 
		                             SYSCON_MS1_PIPE1 | 
                                     SYSCON_MS1_WT0 |  
                                     SYSCON_MS1_IDLE | 
		                             SYSCON_MS0_SLOW  | 
                                     SYSCON_MS0_WT3 |
                                     SYSCON_MS0_IDLE); 

    __builtin_sysreg_write(__SDRCON, SDRCON_INIT | 
    								 SDRCON_RAS2PC5 | 
    								 SDRCON_PC2RAS2 |             
                                     SDRCON_REF3700 | 
                                     SDRCON_PG256 | 
                                     SDRCON_CLAT2 | 
                                     SDRCON_ENBL); 

//---------------------- Enable Interrupts ------------------------------

    temp = __builtin_sysreg_read(__IMASKL);
    temp = temp | INT_DMA0;
    __builtin_sysreg_write(__IMASKL, temp);
    temp = __builtin_sysreg_read(__SQCTL);
    temp = temp | SQCTL_GIE;
    __builtin_sysreg_write(__SQCTL, temp);

//----------------------- Enable FLAG3 Output ---------------------------

    temp = __builtin_sysreg_read(__FLAGREG);
    temp = temp | FLAGREG_FLAG3_EN;                         // Enable output...
    temp = temp & (~SER_ENBL);                              // ...but keep it low for now
    __builtin_sysreg_write(__FLAGREG, temp);

//------------------------ Setup Interrupt ISR --------------------------

    interruptf(SIGDMA0, audio_int);

//-------------------------- Setup DMA TCBs	-----------------------------
//  Setup chain, DMA request and interrupt as follows:
//
//           -> RxLeft -> XmitLeft -> RxRight -> XmitRight -
//          |      |          |                             |
//          |     DMAR       INT                            |
//          |                                               |
//          |_______________________________________________|
//
// change AND mask value to accomodate 19-bits in TS201 DP register, compare DP register for last two params listed below

    RcveDMALSourceTCB.DP = (((long)(&XmitDMALSourceTCB) >> 2) & 0x7FFFF) | TCB_EXTMEM | TCB_NORMAL | TCB_DMAR | TCB_CHAIN;
    RcveDMALDestinTCB.DP = (((long)(&XmitDMALDestinTCB) >> 2) & 0x7FFFF) | TCB_INTMEM | TCB_NORMAL | TCB_DMAR | TCB_CHAIN;
    XmitDMALSourceTCB.DP = (((long)(&RcveDMARSourceTCB) >> 2) & 0x7FFFF) | TCB_INTMEM | TCB_NORMAL | TCB_INT | TCB_CHAIN;
    XmitDMALDestinTCB.DP = (((long)(&RcveDMARDestinTCB) >> 2) & 0x7FFFF) | TCB_EXTMEM | TCB_NORMAL | TCB_INT | TCB_CHAIN;
    RcveDMARSourceTCB.DP = (((long)(&XmitDMARSourceTCB) >> 2) & 0x7FFFF) | TCB_EXTMEM | TCB_NORMAL | TCB_CHAIN;
    RcveDMARDestinTCB.DP = (((long)(&XmitDMARDestinTCB) >> 2) & 0x7FFFF) | TCB_INTMEM | TCB_NORMAL | TCB_CHAIN;
    XmitDMARSourceTCB.DP = (((long)(&RcveDMALSourceTCB) >> 2) & 0x7FFFF) | TCB_INTMEM | TCB_NORMAL | TCB_CHAIN;
    XmitDMARDestinTCB.DP = (((long)(&RcveDMALDestinTCB) >> 2) & 0x7FFFF) | TCB_EXTMEM | TCB_NORMAL | TCB_CHAIN;

//------------------------- Start the DMAs ------------------------------

    SetTCB0(RcveDMALSourceTCB.DI, RcveDMALSourceTCB.DX, RcveDMALSourceTCB.DY, RcveDMALSourceTCB.DP,
            RcveDMALDestinTCB.DI, RcveDMALDestinTCB.DX, RcveDMALDestinTCB.DY, RcveDMALDestinTCB.DP);

//-------------------------- Enable SPORT -------------------------------

    temp = __builtin_sysreg_read(__FLAGREG);
    temp = temp | SER_ENBL;                                 // set the FLAG high now
    __builtin_sysreg_write(__FLAGREG, temp);
}

//***********************************************************************
// Setup DMA TCB0 register (DI_Source, DX_Source, DY_Source, DP_Source
//                          DI_Destin, DX_Destin, DY_Destin, DP_Destin)
//***********************************************************************

void SetTCB0(long DI_Source, long DX_Source, long DY_Source, long DP_Source,
             long DI_Destin, long DX_Destin, long DY_Destin, long DP_Destin)
{
    volatile __builtin_quad TCB_Clear, TCB_Set;

    TCB_Clear = __builtin_compose_128((long long)TCB_DISABLE << 32, 0);
    __builtin_sysreg_write4(__DCS0, TCB_Clear); 
    __builtin_sysreg_write4(__DCD0, TCB_Clear); 
    TCB_Set = __builtin_compose_128(((long long)DX_Source << 32) | DI_Source, ((long long)DP_Source << 32) | DY_Source);
    __builtin_sysreg_write4(__DCS0, TCB_Set); 
    TCB_Set = __builtin_compose_128(((long long)DX_Destin << 32) | DI_Destin, ((long long)DP_Destin << 32) | DY_Destin );
    __builtin_sysreg_write4(__DCD0, TCB_Set); 
}

//***********************************************************************
void Init_ProcessData(void)
{
	Counter0=0;
	Sample=0;
	OutNum=0;
}
//**********************************************