📄 s2440.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 2001. Samsung Electronics, co. ltd All rights reserved.
Module Name:
Abstract:
ARM920(S3C2440) definitions
rev:
2002.5.20 : add define CE_MAJOR_VER == 0x0004 for CE.Net by pcj ( bestworld@samsung.com )
2002.5.16 : change OEM_CLOCK_FREQ value for Audio ( bestworld@samsung.com )
2002.4.3 : S3C2410 Support (SOC)
2002.1.29 : change Timer values
2002.1.29 : CE.NET port
2002.1.22 : Add USBD definitions (kwangyoon LEE, kwangyoon@samsung.com)
Notes:
--*/
#define ARM920
#define USE_AFC 0
// Board timer constants.
//
#define CLK400 1 // 1:400Mhz, 0:533MHz
#define YL_2440_SUPPORT 1 // add by hzh, to support YL-2440
#if CLK400
#ifdef YL_2440_SUPPORT
#define HCLKDIV 4
#define PCLKDIV 8
#define PRESCALER 24
#else
#define HCLKDIV 3
#define PCLKDIV 6
#define PRESCALER 24
#endif
#define S2440FCLK (400000000)
#else // CLK533
#define HCLKDIV 4
#define PCLKDIV 8 // P-clock (PCLK) divisor.
#define S2440FCLK (532800000)
#define PRESCALER 32
#endif
//#define S2410FCLK (203 * 1000 * 1000) // 203MHz (FCLK).
#define S2440HCLK (S2440FCLK / HCLKDIV) // PCLK.
#define S2440PCLK (S2440FCLK / PCLKDIV) // PCLK.
#ifdef YL_2440_SUPPORT
#define S2440UCLK S2440PCLK //UCLK==PCLK, hzh
#else
#define S2440UCLK 50331648 // 48MHz - for serial UARTs.
#endif
#define D1_2 0x0
#define D1_4 0x1
#define D1_8 0x2
#define D1_16 0x3
#define D2 2
#define D4 4
#define D8 8
#define D16 16
#define SYS_TIMER_DIVIDER D2 // D4
#define OEM_CLOCK_FREQ (S2440PCLK / (PRESCALER+1) / SYS_TIMER_DIVIDER)
#define OEM_COUNT_1MS (OEM_CLOCK_FREQ / 1000) // Timer count for 1ms.
#define RESCHED_PERIOD 25 // Reschedule period in ms.
#define RESCHED_INCREMENT (RESCHED_PERIOD * OEM_COUNT_1MS) // Number of ticks per reschedule period.
// Define LCD type of S3C2400X01
#define STN8BPP 1
#define TFT16BPP 2
#define LCDTYPE TFT16BPP // define LCD type as upper definition.
#define TFT240_320 1
#define TFT640_480 4
#define LCD_TYPE TFT240_320
//#define LCD_TYPE TFT640_480
#define AUDIO_CODEC_CLOCK 384
#if (S2440FCLK == 112800000)
#define AUDIO_CODEC_CLOCK 256
#else
#define AUDIO_CODEC_CLOCK 384
#endif
// by pcj for ce.net power management.
#define CE_MAJOR_VER 0x0004
//
// Define S3C2440 Special Registers
//
#ifndef __2440X_H__
#define __2440X_H__
#define CS8900DBG_IOBASE (0xa7000300)
#define CS8900DBG_MEMBASE (0xa6000000)
#ifdef YL_2440_SUPPORT
#define CS8900DBG_IP ((192 << 0) | (168 << 8) | (0 << 16) | (123 << 24))
#else
#define CS8900DBG_IP ((165 << 0) | (213 << 8) | (206 << 16) | (199 << 24))
//#define CS8900DBG_IP ((165 << 0) | (213 << 8) | (172 << 16) | (102 << 24))
#endif
#define CS8900DBG_MASK ((255 << 0) | (255 << 8) | (255 << 16) | (0 << 24))
#define CS8900DBG_MAC0 0x00
#define CS8900DBG_MAC1 0x00
#define CS8900DBG_MAC2 0xf0
#define CS8900DBG_MAC3 0x51
#define CS8900DBG_MAC4 0xff
#define CS8900DBG_MAC5 0xc1
#define CS8900DBG_USHORT(l, h) (l | (h << 8))
//
// Registers : NAND Controller FWOOD 0801
//
#define NAND_BASE 0xB0E00000 // 0x4E000000
#define NFC_BASE 0x90E00000 // 0x4E000000
#define NFC_BASE_PHYSICAL 0x4E000000
typedef struct {
unsigned int rNFCONF; // 0x00
unsigned int rNFCONT; // 0x04 new
unsigned int rNFCMMD; // 0x08 update
unsigned int rNFADDR; // 0x0c
unsigned int rNFDATA; // 0x10
unsigned int rNFMECCD0; // 0x14
unsigned int rNFMECCD1; // 0x18
unsigned int rNFSECCD; // 0x1c
unsigned int rNFSTAT; // 0x20
unsigned int rNFESTAT0; // 0x24
unsigned int rNFESTAT1; // 0x28
unsigned int rNFMECC0; // 0x2c
unsigned int rNFMECC1; // 0x30
unsigned int rNFSECC; // 0x34
unsigned int rNFSBLK; // 0x38
unsigned int rNFEBLK; // 0x3c
} NANDreg;
//
// Memory Controller Register
//
#define MEMCTRL_BASE 0xB0800000 // 0x49000000
typedef struct {
unsigned long rBWSCON; // 0
unsigned long rBANKCON0; // 4
unsigned long rBANKCON1; // 8
unsigned long rBANKCON2; // c
unsigned long rBANKCON3; // 10
unsigned long rBANKCON4; // 1c
unsigned long rBANKCON5; // 18
unsigned long rBANKCON6; // 1c
unsigned long rBANKCON7; // 20
unsigned long rREFRESH; // 24
unsigned long rBANKSIZE; // 28
unsigned long rMRSRB6; // 2c
unsigned long rMRSRB7; // 30
}MEMreg;
//
// Clock & Power Management Special Register
#define CLKPWR_BASE 0xB0C00000 // 0x4C000000
typedef struct {
unsigned long rLOCKTIME;
unsigned long rMPLLCON;
unsigned long rUPLLCON;
unsigned long rCLKCON;
unsigned long rCLKSLOW;
unsigned long rCLKDIVN;
unsigned long rCAMDIVN;
}CLKPWRreg;
// Make sure this matches entry in config.bib
// These buffs are now offset via a constant
#define DMA_BUFFER_BASE 0xAC000000
#define DMA_PHYSICAL_BASE 0x30000000 // S3C2440X01
#define AUDIO_DMA_BUFFER_BASE (DMA_BUFFER_BASE + 0x00002000)
#define AUDIO_DMA_BUFFER_PHYS (DMA_PHYSICAL_BASE + 0x00002000)
#define SDI_DMA_BUFFER_BASE (DMA_BUFFER_BASE + 0x00028000)
#define SDI_DMA_BUFFER_PHYS (DMA_PHYSICAL_BASE + 0x00028000)
#define FRAMEBUF_BASE (DMA_BUFFER_BASE + 0x001d0000)
#define FRAMEBUF_DMA_BASE (DMA_PHYSICAL_BASE + 0x001d0000)
//
// DMA Register
//
#define DMA_BASE 0xB0B00000 // 0x4B0000000
typedef struct {
unsigned int rDISRC0; // 00
unsigned int rDISRCC0; // 04
unsigned int rDIDST0; // 08
unsigned int rDIDSTC0; // 0C
unsigned int rDCON0; // 10
unsigned int rDSTAT0; // 14
unsigned int rDCSRC0; // 18
unsigned int rDCDST0; // 1C
unsigned int rDMASKTRIG0; // 20
unsigned int rPAD1[7]; // 24 - 3C
unsigned int rDISRC1; // 40
unsigned int rDISRCC1; // 44
unsigned int rDIDST1; // 48
unsigned int rDIDSTC1; // 4C
unsigned int rDCON1; // 50
unsigned int rDSTAT1; // 54
unsigned int rDCSRC1; // 58
unsigned int rDCDST1; // 5C
unsigned int rDMASKTRIG1; // 60
unsigned int rPAD2[7]; // 64 - 7C
unsigned int rDISRC2; // 80
unsigned int rDISRCC2; // 84
unsigned int rDIDST2; // 88
unsigned int rDIDSTC2; // 8C
unsigned int rDCON2; // 90
unsigned int rDSTAT2; // 94
unsigned int rDCSRC2; // 98
unsigned int rDCDST2; // 9C
unsigned int rDMASKTRIG2; // A0
unsigned int rPAD3[7]; // A4 - BC
unsigned int rDISRC3; // C0
unsigned int rDISRCC3; // C4
unsigned int rDIDST3; // C8
unsigned int rDIDSTC3; // CC
unsigned int rDCON3; // D0
unsigned int rDSTAT3; // D4
unsigned int rDCSRC3; // D8
unsigned int rDCDST3; // DC
unsigned int rDMASKTRIG3; // E0
}DMAreg;
//
// Register : Camera Interface
//
#define CAM_BASE 0xB0F00000 // 0x4F000000
//
// Register : Camera Interface
//
#define CAM_BASE 0xB0F00000 //0x90F00000 // 0x4F000000
typedef struct {
unsigned int rCISRCFMT; // 00
unsigned int rCIWDOFST; // 04
unsigned int rCIGCTRL; // 08
unsigned int rPAD1; // 0c
unsigned int rPAD2; // 10
unsigned int rPAD3; // 14
unsigned int rCICOYSA1; // 18
unsigned int rCICOYSA2; // 1c
unsigned int rCICOYSA3; // 20
unsigned int rCICOYSA4; // 24
unsigned int rCICOCBSA1; // 28
unsigned int rCICOCBSA2; // 2c
unsigned int rCICOCBSA3; // 30
unsigned int rCICOCBSA4; // 34
unsigned int rCICOCRSA1; // 38
unsigned int rCICOCRSA2; // 3c
unsigned int rCICOCRSA3; // 40
unsigned int rCICOCRSA4; // 44
unsigned int rCICOTRGFMT; // 48
unsigned int rCICOCTRL; // 4c
unsigned int rCICOSCPRERATIO; // 50
unsigned int rCICOSCPREDST; // 54
unsigned int rCICOSCCTRL; // 58
unsigned int rCICOTAREA; // 5c
unsigned int rPAD4; // 60
unsigned int rCICOSTATUS; // 64
unsigned int rPAD5; // 68
unsigned int rCIPRCLRSA1; // 6c
unsigned int rCIPRCLRSA2; // 70
unsigned int rCIPRCLRSA3; // 74
unsigned int rCIPRCLRSA4; // 78
unsigned int rCIPRTRGFMT; // 7c
unsigned int rCIPRCTRL; // 80
unsigned int rCIPRSCPRERATIO; // 84
unsigned int rCIPRSCPREDST; // 88
unsigned int rCIPRSCCTRL; // 8c
unsigned int rCIPRTAREA; // 90
unsigned int rPAD6; // 94
unsigned int rCIPRSTATUS; // 98
unsigned int rPAD7; // 9c
unsigned int rCIIMGCPT; // a0
} CAMreg;
/*
typedef struct {
unsigned int rASIZE;
unsigned int rSTAY1;
unsigned int rSTAY2;
unsigned int rSTAY3;
unsigned int rSTAY4;
unsigned int rAYBURST;
unsigned int rACBBURST;
unsigned int rACRBURST;
unsigned int rBSIZE;
unsigned int rSTBY1;
unsigned int rSTBY2;
unsigned int rSTBY3;
unsigned int rSTBY4;
unsigned int rBYBURST;
unsigned int rBCBBURST;
unsigned int rBCRBURST;
unsigned int rADISTWIDTH;
unsigned int rBDISTWIDTH;
unsigned int rTmp; // 0x4F000048
unsigned int rYRATIO;
unsigned int rCRATIO;
unsigned int rYORIGINAL;
unsigned int rTmp1; // 0x4F000058
unsigned int rCORIGINAL; // 0x4F00005C
unsigned int rTp1; // 0x4F000060
unsigned int rTp2; // 0x4F000064
unsigned int rTp3; // 0x4F000068
unsigned int rTp4; // 0x4F00006C
unsigned int rTp5; // 0x4F000070
unsigned int rSTACB1; // 0x4F000074
unsigned int rSTACB2;
unsigned int rSTACB3;
unsigned int rSTACB4;
unsigned int rSTACR1;
unsigned int rSTACR2;
unsigned int rSTACR3;
unsigned int rSTACR4;
unsigned int rTmp2; // 0x4F000094
unsigned int rTmp3; // 0x4F000098
unsigned int rSTBCB1;
unsigned int rSTBCB2;
unsigned int rSTBCB3;
unsigned int rSTBCB4;
unsigned int rSTBCR1;
unsigned int rSTBCR2;
unsigned int rSTBCR3;
unsigned int rSTBCR4;
unsigned int rCTRL_C;
}CAMreg;
*/
// camera
// read only register
typedef struct {
unsigned int rRDSTAT; // 0x4F000000
unsigned int rTmp4; // 0x4F000004
unsigned int rTmp5; // 0x4F000008
unsigned int rTmp6; // 0x4F00000C
unsigned int rTmp7; // 0x4F000010
unsigned int rRDSTAY; // 0x4F000014
unsigned int rRDSTACB;
unsigned int rRDSTACR;
unsigned int rRDSTACB1;
unsigned int rRDSTACR1;
unsigned int rRDSTBY1;
unsigned int rRDSTBY2;
unsigned int rRDSTBY3;
unsigned int rRDSTBY4;
unsigned int rRDSTBY;
unsigned int rRDSTBCB;
unsigned int rRDSTBCR; // 0x4F000040
unsigned int rRDSTBCB1;
unsigned int rRDSTBCR1;
unsigned int rRDADISTWIDTH;
unsigned int rRDBDISTWIDTH;
}CAM_Rreg;
//
// Registers : I/O port
//
#define IOP_BASE 0xB1600000 // 0x56000000
typedef struct {
unsigned int rGPACON; // 00
unsigned int rGPADAT;
unsigned int rPAD1[2];
unsigned int rGPBCON; // 10
unsigned int rGPBDAT;
unsigned int rGPBUP;
unsigned int rPAD2;
unsigned int rGPCCON; // 20
unsigned int rGPCDAT;
unsigned int rGPCUP;
unsigned int rPAD3;
unsigned int rGPDCON; // 30
unsigned int rGPDDAT;
unsigned int rGPDUP;
unsigned int rPAD4;
unsigned int rGPECON; // 40
unsigned int rGPEDAT;
unsigned int rGPEUP;
unsigned int rPAD5;
unsigned int rGPFCON; // 50
unsigned int rGPFDAT;
unsigned int rGPFUP;
unsigned int rPAD6;
unsigned int rGPGCON; // 60
unsigned int rGPGDAT;
unsigned int rGPGUP;
unsigned int rPAD7;
unsigned int rGPHCON; // 70
unsigned int rGPHDAT;
unsigned int rGPHUP;
unsigned int rPAD8;
unsigned int rMISCCR; // 80
unsigned int rDCKCON;
unsigned int rEXTINT0;
unsigned int rEXTINT1;
unsigned int rEXTINT2; // 90
unsigned int rEINTFLT0;
unsigned int rEINTFLT1;
unsigned int rEINTFLT2;
unsigned int rEINTFLT3; // A0
unsigned int rEINTMASK;
unsigned int rEINTPEND;
unsigned int rGSTATUS0; // AC
unsigned int rGSTATUS1; // B0
unsigned int rGSTATUS2; // B4 ;;; SHL
unsigned int rGSTATUS3; // B8
unsigned int rGSTATUS4; // BC
unsigned int rFLTOUT; // C0
unsigned int rDSC0;
unsigned int rDSC1;
unsigned int rMSLCON;
unsigned int rGPJCON; // D0
unsigned int rGPJDAT;
unsigned int rGPJUP;
unsigned int rPAD9;
}IOPreg;
//
// Registers : PWM
//
#define PWM_BASE 0xB1100000 // 0x51000000
typedef struct {
unsigned int rTCFG0;
unsigned int rTCFG1;
unsigned int rTCON;
unsigned int rTCNTB0;
unsigned int rTCMPB0;
unsigned int rTCNTO0;
unsigned int rTCNTB1;
unsigned int rTCMPB1;
unsigned int rTCNTO1;
unsigned int rTCNTB2;
unsigned int rTCMPB2;
unsigned int rTCNTO2;
unsigned int rTCNTB3;
unsigned int rTCMPB3;
unsigned int rTCNTO3;
unsigned int rTCNTB4;
unsigned int rTCNTO4;
}PWMreg ;
//
// Registers : UART
//
#define UART0_BASE 0xB1000000 // 0x50000000
#define UART1_BASE 0xB1004000
#define UART2_BASE 0xB1008000
typedef struct {
unsigned int rULCON;
unsigned int rUCON;
unsigned int rUFCON;
unsigned int rUMCON;
unsigned int rUTRSTAT;
unsigned int rUERSTAT;
unsigned int rUFSTAT;
unsigned int rUMSTAT;
unsigned int rUTXH;
unsigned int rURXH;
unsigned int rUBRDIV;
}UART0reg, UART1reg, UART2reg, UARTreg, S2440_UART_REG, *PS2440_UART_REG;
// 2440 USB DEVICE Function (Written by Seung-han, Lim)
// Little-Endian
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