checksum_task_logic.v.bak

altera 的示例ip

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module checksum_task_logic (
		gls_clk,
		gls_reset_n,
		go,
		data_in_ready,
		data_to_process,
		result
		
		);
	
		input gls_clk;
		input gls_reset_n;
		
		input go;
		
		input data_in_ready;
		input [31:0]data_to_process;
		
		output [15:0]result;
		
reg [31:0] data_in_reg;
reg [31:0] sum_reg;
reg data_in_ready_delay;

wire [31:0] sum_1;
wire [31:0] sum_2;
wire [31:0] sum_3;
wire [31:0] next_sum_reg;



// delay register for data_in_ready
always@(posedge gls_clk or negedge gls_reset_n)
begin
    if(gls_reset_n == 1'b0) 
		begin
			data_in_ready_delay <= 1'b0;
    	end
    else  
		begin
			data_in_ready_delay <= data_in_ready;
		end
    
end // always@ 

//Write to the data_in register 
always@(posedge gls_clk or negedge gls_reset_n)
begin
    if(gls_reset_n == 1'b0) 
		begin
			data_in_reg <= 32'h00000000;
    	end
    else  
		begin
			data_in_reg <= data_to_process;
		end
    
end // always@ 

// first adder stage (16-bits) fold upper and lower half
assign sum_1 = data_in_reg[31:16] + data_in_reg[15:0];

// second adder state (32-bits) of sum_1 and previously stored sum (sum_reg)
assign next_sum_reg = sum_1 + sum_reg;

// Write to the sum register the next value
always@(posedge gls_clk or negedge gls_reset_n)
begin
    if(gls_reset_n == 1'b0) 
		begin
		sum_reg <= 32'h00000000;
    	end
    else if(go)						// clears sum_reg at start of checksum calculation
		begin
		sum_reg <= 32'h00000000;
		end
    else if(data_in_ready_delay == 1'b1)
		begin
	   		sum_reg <= next_sum_reg;
		end
	else 
		begin
	   		sum_reg <= sum_reg;
		end
end // always@

// Fold in upper (carry count) and lower half of sum register	
assign sum_2 = sum_reg[31:16] + sum_reg[15:0];

// Fold in upper (possible carry) and lower half of sum_2
assign sum_3 = sum_2[31:16] + sum_2[15:0];

// Invert the sum (one's complement) for result
assign result = { ~(sum_3[15:0]) };

endmodule