📄 fw.lst
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591 000001a0 ; * CPUPowerOff - OFF button handler(Called from OEMPowerOff() in cfw.c)
592 000001a0 ; * This routine is invoked when the OFF button is pressed. It is responsible
593 000001a0 ; * for any final power off state and putting the cpu into standby.
594 000001a0 ; *
595 000001a0 ; * Entry none
596 000001a0 ; * Exit none
597 000001a0 ; * Uses r0-r3
598 000001a0 ; *
599 000001a0
600 000001a0 LEAF_ENTRY CPUPowerOff
601 000001a0
602 000001a0 ; 1. Push SVC state onto our stack
603 000001a0 e92d1ff0 stmdb sp!, {r4-r12}
604 000001a4 e92d4000 stmdb sp!, {lr}
605 000001a8
606 000001a8 ; VLED_ON 0x0
607 000001a8 ; 2. Save MMU & CPU Register to RAM
608 000001a8 e59f321c ldr r3, =SLEEPDATA_BASE_VIRTUAL ; base of Sleep mode storage
609 000001ac
610 000001ac e59f224c ldr r2, =Awake_address ; store Virtual return address
611 000001b0 e4832004 str r2, [r3], #4
612 000001b4 ee112f10 mrc p15, 0, r2, c1, c0, 0 ; load r2 with MMU Control
613 000001b8 e59f0210 ldr r0, =MMU_CTL_MASK ; mask off the undefined bits
614 000001bc e1c22000 bic r2, r2, r0
615 000001c0 e4832004 str r2, [r3], #4 ; store MMU Control data
616 000001c4
617 000001c4 ee122f10 mrc p15, 0, r2, c2, c0, 0 ; load r2 with TTB address.
618 000001c8 e59f0204 ldr r0, =MMU_TTB_MASK ; mask off the undefined bits
619 000001cc e1c22000 bic r2, r2, r0
620 000001d0 e4832004 str r2, [r3], #4 ; store TTB address
621 000001d4
622 000001d4 ee132f10 mrc p15, 0, r2, c3, c0, 0 ; load r2 with domain access control.
623 000001d8 e4832004 str r2, [r3], #4 ; store domain access control
624 000001dc
625 000001dc e483d004 str sp, [r3], #4 ; store SVC stack pointer
626 000001e0
627 000001e0 e14f2000 mrs r2, spsr
628 000001e4 e4832004 str r2, [r3], #4 ; store SVC status register
629 000001e8
630 000001e8 e3a010d1 mov r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts
631 000001ec e129f001 msr cpsr, r1
632 000001f0 e14f2000 mrs r2, spsr
633 000001f4 e8a37f04 stmia r3!, {r2, r8-r12, sp, lr} ; store the FIQ mode registers
634 000001f8
635 000001f8 e3a010d7 mov r1, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Enter ABT mode, no interrupts
636 000001fc e129f001 msr cpsr, r1
637 00000200 e14f0000 mrs r0, spsr
638 00000204 e8a36001 stmia r3!, {r0, sp, lr} ; store the ABT mode Registers
639 00000208
640 00000208 e3a010d2 mov r1, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Enter IRQ mode, no interrupts
641 0000020c e129f001 msr cpsr, r1
642 00000210 e14f0000 mrs r0, spsr
643 00000214 e8a36001 stmia r3!, {r0, sp, lr} ; store the IRQ Mode Registers
644 00000218
645 00000218 e3a010db mov r1, #Mode_UND:OR:I_Bit:OR:F_Bit ; Enter UND mode, no interrupts
646 0000021c e129f001 msr cpsr, r1
647 00000220 e14f0000 mrs r0, spsr
648 00000224 e8a36001 stmia r3!, {r0, sp, lr} ; store the UND mode Registers
649 00000228
650 00000228 e3a010df mov r1, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Enter SYS mode, no interrupts
651 0000022c e129f001 msr cpsr, r1
652 00000230 e8a36000 stmia r3!, {sp, lr} ; store the SYS mode Registers
653 00000234
654 00000234 e3a010d3 mov r1, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Back to SVC mode, no interrupts
655 00000238 e129f001 msr cpsr, r1
656 0000023c
657 0000023c ; 3. do Checksum on the Sleepdata
658 0000023c e59f3188 ldr r3, =SLEEPDATA_BASE_VIRTUAL ; get pointer to SLEEPDATA
659 00000240 e3a02000 mov r2, #0
660 00000244 e3a00019 ldr r0, =SLEEPDATA_SIZE ; get size of data structure (in words)
661 00000248 30
662 00000248 e4931004 ldr r1, [r3], #4
663 0000024c e2011001 and r1, r1, #0x1
664 00000250 e1a01f81 mov r1, r1, LSL #31
665 00000254 e18110a1 orr r1, r1, r1, LSR #1
666 00000258 e0822001 add r2, r2, r1
667 0000025c e2500001 subs r0, r0, #1
668 00000260 1afffff8 bne %b30
669 00000264
670 00000264
671 00000264 e59f016c ldr r0, =vGPIOBASE
672 00000268 e58020b8 str r2, [r0, #oGSTATUS3] ; Store in Power Manager Scratch pad register
673 0000026c
674 0000026c ; 4. Interrupt Disable
675 0000026c e59f0168 ldr r0, =vINTBASE
676 00000270 e3e02000 mvn r2, #0
677 00000274 e5802008 str r2, [r0, #oINTMSK]
678 00000278 e5802000 str r2, [r0, #oSRCPND]
679 0000027c e5802010 str r2, [r0, #oINTPND]
680 00000280
681 00000280 ; 5. Cache Flush
682 00000280 eb000000 bl TLBClear
683 00000284 eb000000 bl FlushICache
684 00000288 eb000000 bl FlushDCache
685 0000028c
686 0000028c ; 6. Setting Wakeup External Interrupt(EINT0,1,2) Mode
687 0000028c e59f0144 ldr r0, =vGPIOBASE
688 00000290
689 00000290 e59f1148 ldr r1, =0x550a
690 00000294 e5801050 str r1, [r0, #oGPFCON]
691 00000298
692 00000298 e59f1144 ldr r1, =0x55550100
693 0000029c e5801060 str r1, [r0, #oGPGCON]
694 000002a0
695 000002a0 ; 7. Go to Power-Off Mode
696 000002a0 e59f014c ldr r0, = vMPLLCON
697 000002a4 e59f114c ldr r1, = PLLVAL
698 000002a8 e5801000 str r1, [r0]
699 000002ac
700 000002ac e59f0114 ldr r0, =vREFRESH
701 000002b0 e5901000 ldr r1, [r0] ; r1=rREFRESH
702 000002b4 e3811501 orr r1, r1, #(1 << 22)
703 000002b8
704 000002b8 e59f2128 ldr r2, =vMISCCR
705 000002bc e5923000 ldr r3, [r2]
706 000002c0 e383380e orr r3, r3, #(7<<17) ; Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
707 000002c4
708 000002c4 e59f4120 ldr r4, =vCLKCON
709 000002c8 e59f5120 ldr r5, =0x7fff8 ; Power Off Mode
710 000002cc
711 000002cc ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
712 000002cc ; WinCE 3.00 assembler has some problem about ALIGN instruction.
713 000002cc ; Sometimes it is not working in cache mode. So I modify to jump to ROM area.
714 000002cc ; If the rom is EBOOT, the target address is 0x92001004.
715 000002cc ; Else if the rom is NAND, the target address is 0x92000004.
716 000002cc
717 000002cc e3a084ea ldr r8, =0xEA000000
718 000002d0 e2888e3f add r8, r8, #0x3f0
719 000002d4 e288800e add r8, r8, #0xe ; make value to 0xEA0003FE
720 000002d8
721 000002d8 e3a06492 ldr r6, =0x92000000 ; make address to 0x9200 1004 or 0x9200 0004
722 000002dc
723 000002dc e5967000 ldr r7, [r6] ; Check ROM Address data, if 0xEA0003FE, it is EBOOT
724 000002e0 e1570008 cmp r7, r8
725 000002e4 1a000000 bne %f50
726 000002e8 e2866a01 add r6, r6, #0x1000 ; Because eboot startup code is located at 0x1000.
727 000002ec 50
728 000002ec e2866004 add r6, r6, #0x4 ;
729 000002f0 e1a0f006 mov pc, r6 ; jump to Power off code in ROM
730 000002f4 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
731 000002f4
732 000002f4 ea000001 b SelfRefreshAndPowerOff
733 000002f8
734 000002f8 00 00 00 ALIGN 32 ; for I-Cache Line(32Byte, 8 Word)
00 00 00
00 00
735 00000300
736 00000300 SelfRefreshAndPowerOff ; run with Instruction Cache's code
737 00000300 e5801000 str r1, [r0] ; Enable SDRAM self-refresh
738 00000304 e5823000 str r3, [r2] ; MISCCR Setting
739 00000308 e5845000 str r5, [r4] ; Power Off !!
740 0000030c eafffffe b .
741 00000310
742 00000310
743 00000310 ; This point is called from EBOOT's startup code(MMU is enabled)
744 00000310 ; in this routine, left information(REGs, INTMSK, INTSUBMSK ...)
745 00000310
746 00000310 Awake_address
747 00000310
748 00000310 ; 1. Recover CPU Registers
749 00000310
750 00000310 e59f30b4 ldr r3, =SLEEPDATA_BASE_VIRTUAL ; Sleep mode information data structure
751 00000314 e2832018 add r2, r3, #SleepState_FIQ_SPSR
752 00000318 e3a010d1 mov r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts
753 0000031c e129f001 msr cpsr, r1
754 00000320 e4920004 ldr r0, [r2], #4
755 00000324 e169f000 msr spsr, r0
756 00000328 e4928004 ldr r8, [r2], #4
757 0000032c e4929004 ldr r9, [r2], #4
758 00000330 e492a004 ldr r10, [r2], #4
759 00000334 e492b004 ldr r11, [r2], #4
760 00000338 e492c004 ldr r12, [r2], #4
761 0000033c e492d004 ldr sp, [r2], #4
762 00000340 e492e004 ldr lr, [r2], #4
763 00000344
764 00000344 e3a010d7 mov r1, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Enter ABT mode, no interrupts
765 00000348 e129f001 msr cpsr, r1
766 0000034c e4920004 ldr r0, [r2], #4
767 00000350 e169f000 msr spsr, r0
768 00000354 e492d004 ldr sp, [r2], #4
769 00000358 e492e004 ldr lr, [r2], #4
770 0000035c
771 0000035c e3a010d2 mov r1, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Enter IRQ mode, no interrupts
772 00000360 e129f001 msr cpsr, r1
773 00000364 e4920004 ldr r0, [r2], #4
774 00000368 e169f000 msr spsr, r0
775 0000036c e492d004 ldr sp, [r2], #4
776 00000370 e492e004 ldr lr, [r2], #4
777 00000374
778 00000374 e3a010db mov r1, #Mode_UND:OR:I_Bit:OR:F_Bit ; Enter UND mode, no interrupts
779 00000378 e129f001 msr cpsr, r1
780 0000037c e4920004 ldr r0, [r2], #4
781 00000380 e169f000 msr spsr, r0
782 00000384 e492d004 ldr sp, [r2], #4
783 00000388 e492e004 ldr lr, [r2], #4
784 0000038c
785 0000038c e3a010df mov r1, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Enter SYS mode, no interrupts
786 00000390 e129f001 msr cpsr, r1
787 00000394 e492d004 ldr sp, [r2], #4
788 00000398 e592e000 ldr lr, [r2]
789 0000039c
790 0000039c e3a010d3 mov r1, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Enter SVC mode, no interrupts
791 000003a0 e129f001 msr cpsr, r1
792 000003a4 e5930014 ldr r0, [r3, #SleepState_SVC_SPSR]
793 000003a8 e169f000 msr spsr, r0
794 000003ac
795 000003ac ; 2. Recover Last mode's REG's, & go back to caller of CPUPowerOff()
796 000003ac
797 000003ac e593d010 ldr sp, [r3, #SleepState_SVC_SP]
798 000003b0 e49de004 ldr lr, [sp], #4
799 000003b4 e8bd1ff0 ldmia sp!, {r4-r12}
800 000003b8 e1a0f00e mov pc, lr ; and now back to our sponsors
801 000003bc
802 000003bc ;
803 000003bc ; MMU_WaitForInterrupt() from 2410slib.s (in bsp/others/test2410_r11 dirs)
804 000003bc ;
805 000003bc ;void MMU_WaitForInterrupt(void)
806 000003bc EXPORT MMU_WaitForInterrupt
807 000003bc MMU_WaitForInterrupt
808 000003bc ee070f90 mcr p15,0,r0,c7,c0,4
809 000003c0 e1a0f00e mov pc, lr ;MOV_PC_LR
810 000003c4
811 000003c4 END
812 000003c4 b1300000 *literal pool: constant
812 000003c8 b0800024 *literal pool: constant
812 000003cc a0008000 *literal pool: constant
812 000003d0 3fff0000 *literal pool: constant
812 000003d4 00003fff *literal pool: constant
812 000003d8 b1600000 *literal pool: constant
812 000003dc b0a00000 *literal pool: constant
812 000003e0 0000550a *literal pool: constant
812 000003e4 55550100 *literal pool: constant
812 000003e8 b1600080 *literal pool: constant
812 000003ec b0c0000c *literal pool: constant
812 000003f0 0007fff8 *literal pool: constant
812 000003f4 b0c00004 *literal pool: constant
812 000003f8 000a1031 *literal pool: constant
812 000003fc 00000074 *literal pool: symbol: PhysicalStart + 0x0
812 00000400 00000310 *literal pool: symbol: Awake_address + 0x0
812 00000404 00000000 *literal pool: unused space
Assembly terminated, errors: 0, warnings: 0
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