📄 fw.lst
字号:
00000001
63 00000360 91900000 DCD 0x91900000, 0x59000000, 1 ; SPI register
59000000
00000001
64 0000036c 91a00000 DCD 0x91A00000, 0x5A000000, 1 ; SD Interface register
5a000000
00000001
65 00000378 92000000 DCD 0x92000000, 0x00000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 0
00000000
00000020
66 00000384 00000000 DCD 0x00000000, 0x00000000, 0 ; End of Table (MB MUST BE ZERO!)
00000000
00000000
67 00000390
68 00000390 END
368 00000390
369 00000390 TEXTAREA
370 00000000
371 00000000
372 00000000 ;**
373 00000000 ; * CPUPowerWDReset - Software reset routine. Use watchdog timer and SDRAM to self-refresh mode.
374 00000000 ; *
375 00000000 ; * Entry none
376 00000000 ; * Exit none
377 00000000 ; * Uses r0-r3
378 00000000 ; *
379 00000000 LEAF_ENTRY CPUPowerWDReset
380 00000000
381 00000000 ; VLED_ON 0xb
382 00000000
383 00000000 ;Watchdog reset enable.
384 00000000 e59f13bc ldr r1, =vWTCON
385 00000004 e5910000 ldr r0, [r1]
386 00000008 e3800020 orr r0, r0, #(1<<5) ; Enable watchdog timer.
387 0000000c e5810000 str r0, [r1]
388 00000010
389 00000010 e59f03b0 ldr r0, =vREFRESH
390 00000014 e5901000 ldr r1, [r0] ; r1=rREFRESH
391 00000018 e3811501 orr r1, r1, #(1 << 22)
392 0000001c
393 0000001c ;Set memory control self-refersh
394 0000001c e59f03a4 ldr r0,=vREFRESH
395 00000020 e5903000 ldr r3,[r0] ;r3=rREFRESH, may fill TLB
396 00000024 e3833501 orr r3, r3, #BIT_SELFREFRESH
397 00000028 ea000004 b %F1
398 0000002c 00 00 00 ALIGN 32 ;The following instructions will be in I-Cache
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00
399 00000040 1
400 00000040 e5803000 str r3, [r0] ;Enable SDRAM self-refresh
401 00000044 eafffffe b .
402 00000048
403 00000048
404 00000048 ;**
405 00000048 ; * CPUPowerReset - Software reset routine. Just jump to StartUp in this file.
406 00000048 ; *
407 00000048 ; * Entry none
408 00000048 ; * Exit none
409 00000048 ; * Uses r0-r3
410 00000048 ; *
411 00000048
412 00000048 LEAF_ENTRY CPUPowerReset
413 00000048 e59f337c ldr r3, =SLEEPDATA_BASE_VIRTUAL ; base of Sleep mode storage
414 0000004c e3a0230e mov r2, #0x38000000 ; store Virtual return address
415 00000050 e4832004 str r2, [r3], #4
416 00000054
417 00000054 ; Disable MMU
418 00000054 e59f23a0 ldr r2, = PhysicalStart
419 00000058 e3a03205 ldr r3, = (0x80000000 - 0x30000000)
420 0000005c e0422003 sub r2, r2, r3
421 00000060
422 00000060 e3a01070 mov r1, #0x0070 ; Disable MMU
423 00000064 ee011f10 mcr p15, 0, r1, c1, c0, 0
424 00000068 e1a00000 nop
425 0000006c e1a0f002 mov pc, r2 ; Jump to PStart
426 00000070 e1a00000 nop
427 00000074
428 00000074 ; MMU & caches now disabled.
429 00000074 PhysicalStart
430 00000074 eb000000 bl TLBClear
431 00000078 eb000000 bl FlushICache
432 0000007c eb000000 bl FlushDCache
433 00000080
434 00000080 e3a02a41 ldr r2, =0x41000 ; offset into the RAM
435 00000084 e2822203 add r2, r2, #0x30000000 ; add physical base
436 00000088 e1a0f002 mov pc, r2 ; & jump to StartUp address
437 0000008c
438 0000008c
439 0000008c
440 0000008c ;**
441 0000008c ; * EmergencyCPUPowerOff - Emergency condition ( fast poweroff ).
442 0000008c ; *
443 0000008c ; * Entry none
444 0000008c ; * Exit none
445 0000008c ; * Uses r0-r3
446 0000008c ; *
447 0000008c LEAF_ENTRY EmergencyCPUPowerOff
448 0000008c
449 0000008c ; 1. Push SVC state onto our stack
450 0000008c e92d1ff0 stmdb sp!, {r4-r12}
451 00000090 e92d4000 stmdb sp!, {lr}
452 00000094
453 00000094 ; VLED_ON 0x0
454 00000094 ; 2. Save MMU & CPU Register to RAM
455 00000094 e59f3330 ldr r3, =SLEEPDATA_BASE_VIRTUAL ; base of Sleep mode storage
456 00000098
457 00000098 e59f2360 ldr r2, =Awake_address ; store Virtual return address
458 0000009c e4832004 str r2, [r3], #4
459 000000a0 ee112f10 mrc p15, 0, r2, c1, c0, 0 ; load r2 with MMU Control
460 000000a4 e59f0324 ldr r0, =MMU_CTL_MASK ; mask off the undefined bits
461 000000a8 e1c22000 bic r2, r2, r0
462 000000ac e4832004 str r2, [r3], #4 ; store MMU Control data
463 000000b0
464 000000b0 ee122f10 mrc p15, 0, r2, c2, c0, 0 ; load r2 with TTB address.
465 000000b4 e59f0318 ldr r0, =MMU_TTB_MASK ; mask off the undefined bits
466 000000b8 e1c22000 bic r2, r2, r0
467 000000bc e4832004 str r2, [r3], #4 ; store TTB address
468 000000c0
469 000000c0 ee132f10 mrc p15, 0, r2, c3, c0, 0 ; load r2 with domain access control.
470 000000c4 e4832004 str r2, [r3], #4 ; store domain access control
471 000000c8
472 000000c8 e483d004 str sp, [r3], #4 ; store SVC stack pointer
473 000000cc
474 000000cc e14f2000 mrs r2, spsr
475 000000d0 e4832004 str r2, [r3], #4 ; store SVC status register
476 000000d4
477 000000d4 e3a010d1 mov r1, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; Enter FIQ mode, no interrupts
478 000000d8 e129f001 msr cpsr, r1
479 000000dc e14f2000 mrs r2, spsr
480 000000e0 e8a37f04 stmia r3!, {r2, r8-r12, sp, lr} ; store the FIQ mode registers
481 000000e4
482 000000e4 e3a010d7 mov r1, #Mode_ABT:OR:I_Bit:OR:F_Bit ; Enter ABT mode, no interrupts
483 000000e8 e129f001 msr cpsr, r1
484 000000ec e14f0000 mrs r0, spsr
485 000000f0 e8a36001 stmia r3!, {r0, sp, lr} ; store the ABT mode Registers
486 000000f4
487 000000f4 e3a010d2 mov r1, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; Enter IRQ mode, no interrupts
488 000000f8 e129f001 msr cpsr, r1
489 000000fc e14f0000 mrs r0, spsr
490 00000100 e8a36001 stmia r3!, {r0, sp, lr} ; store the IRQ Mode Registers
491 00000104
492 00000104 e3a010db mov r1, #Mode_UND:OR:I_Bit:OR:F_Bit ; Enter UND mode, no interrupts
493 00000108 e129f001 msr cpsr, r1
494 0000010c e14f0000 mrs r0, spsr
495 00000110 e8a36001 stmia r3!, {r0, sp, lr} ; store the UND mode Registers
496 00000114
497 00000114 e3a010df mov r1, #Mode_SYS:OR:I_Bit:OR:F_Bit ; Enter SYS mode, no interrupts
498 00000118 e129f001 msr cpsr, r1
499 0000011c e8a36000 stmia r3!, {sp, lr} ; store the SYS mode Registers
500 00000120
501 00000120 e3a010d3 mov r1, #Mode_SVC:OR:I_Bit:OR:F_Bit ; Back to SVC mode, no interrupts
502 00000124 e129f001 msr cpsr, r1
503 00000128
504 00000128 ; 3. do Checksum on the Sleepdata
505 00000128 ; ldr r3, =SLEEPDATA_BASE_VIRTUAL ; get pointer to SLEEPDATA
506 00000128 ; mov r2, #0
507 00000128 ; ldr r0, =SLEEPDATA_SIZE ; get size of data structure (in words)
508 00000128 ;30
509 00000128 ; ldr r1, [r3], #4
510 00000128 ; and r1, r1, #0x1
511 00000128 ; mov r1, r1, LSL #31
512 00000128 ; orr r1, r1, r1, LSR #1
513 00000128 ; add r2, r2, r1
514 00000128 ; subs r0, r0, #1
515 00000128 ; bne %b30
516 00000128
517 00000128
518 00000128 e59f02a8 ldr r0, =vGPIOBASE
519 0000012c e58020b8 str r2, [r0, #oGSTATUS3] ; Store in Power Manager Scratch pad register
520 00000130
521 00000130 ; VLED_ON 0xb - 24uS
522 00000130 ; 4. Interrupt Disable
523 00000130 e59f02a4 ldr r0, =vINTBASE
524 00000134 e3e02000 mvn r2, #0
525 00000138 e5802008 str r2, [r0, #oINTMSK]
526 0000013c e5802000 str r2, [r0, #oSRCPND]
527 00000140 e5802010 str r2, [r0, #oINTPND]
528 00000144
529 00000144 ; 5. Cache Flush
530 00000144 ; bl TLBClear
531 00000144 ; bl FlushICache
532 00000144 ; bl FlushDCache
533 00000144
534 00000144 ; VLED_ON 0xb - 28uS
535 00000144
536 00000144 ; 6. Setting Wakeup External Interrupt(EINT0,1,2) Mode
537 00000144 e59f028c ldr r0, =vGPIOBASE
538 00000148
539 00000148 e59f1290 ldr r1, =0x550a
540 0000014c e5801050 str r1, [r0, #oGPFCON]
541 00000150
542 00000150 e59f128c ldr r1, =0x55550100
543 00000154 e5801060 str r1, [r0, #oGPGCON]
544 00000158
545 00000158 ; VLED_ON 0xb - 28uS
546 00000158
547 00000158 ; 7. Go to Power-Off Mode
548 00000158 ; ldr r0, = vMPLLCON
549 00000158 ; ldr r1, = PLLVAL
550 00000158 ; str r1, [r0]
551 00000158
552 00000158 ; VLED_ON 0xb ;- 364uS
553 00000158
554 00000158 e59f0268 ldr r0, =vREFRESH
555 0000015c e5901000 ldr r1, [r0] ; r1=rREFRESH
556 00000160 e3811501 orr r1, r1, #(1 << 22)
557 00000164
558 00000164 e59f227c ldr r2, =vMISCCR
559 00000168 e5923000 ldr r3, [r2]
560 0000016c e383380e orr r3, r3, #(7<<17) ; Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
561 00000170
562 00000170 e59f4274 ldr r4, =vCLKCON
563 00000174 e59f5274 ldr r5, =0x7fff8 ; Power Off Mode
564 00000178
565 00000178
566 00000178 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
567 00000178 ; WinCE 3.00 assembler has some problem about ALIGN instruction.
568 00000178 ; Sometimes it is not working in cache mode. So I modify to jump to ROM area.
569 00000178 ; If the rom is EBOOT, the target address is 0x92001004.
570 00000178 ; Else if the rom is NAND, the target address is 0x92000004.
571 00000178
572 00000178 e3a084ea ldr r8, =0xEA000000
573 0000017c e2888e3f add r8, r8, #0x3f0
574 00000180 e288800e add r8, r8, #0xe ; make value to 0xEA0003FE
575 00000184
576 00000184 e3a06492 ldr r6, =0x92000000 ; make address to 0x9200 1004 or 0x9200 0004
577 00000188
578 00000188 e5967000 ldr r7, [r6] ; Check ROM Address data, if 0xEA0003FE, it is EBOOT
579 0000018c e1570008 cmp r7, r8
580 00000190 1a000000 bne %f50
581 00000194 e2866a01 add r6, r6, #0x1000 ; Because eboot startup code is located at 0x1000.
582 00000198 50
583 00000198 e2866004 add r6, r6, #0x4 ;
584 0000019c e1a0f006 mov pc, r6 ; jump to Power off code in ROM
585 000001a0 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
586 000001a0
587 000001a0
588 000001a0
589 000001a0
590 000001a0 ;**
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -