📄 fw.lst
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249 0000010c e1a0f002 mov pc, r2 ; & jump to StartUp address
250 00000110 ; mov pc, #0x30000000 ; Start address
251 00000110 eafffffe b .
252 00000114
253 00000114
254 00000114 ; Case of Power-off reset
255 00000114 3
256 00000114 e59f10f8 ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
257 00000118 e5910000 ldr r0, [r1] ; I don't know why, Just fallow Sample Code.
258 0000011c e3c0080e bic r0, r0, #(7 << 17) ; SCLK0:0->SCLK, SCLK1:0->SCLK, SCKE:L->H
259 00000120 e5810000 str r0, [r1]
260 00000124 ; - - - - - - - - - - - - - - - - - - - - - - -
261 00000124 ; Add for Power Management
262 00000124 ; :::::::::::::::::::::::::::::::::::::::::::::
263 00000124
264 00000124 ; Normal Mode
265 00000124 4
266 00000124 e28f00f8 add r0, pc, #SMRDATA - (. + 8)
267 00000128 e3a01312 ldr r1, = BWSCON ; BWSCON Address
268 0000012c e2802034 add r2, r0, #52 ; End address of SMRDATA
269 00000130 1
270 00000130 e4903004 ldr r3, [r0], #4
271 00000134 e4813004 str r3, [r1], #4
272 00000138 e1520000 cmp r2, r0
273 0000013c 1afffffb bne %B1
274 00000140
275 00000140
276 00000140 ; :::::::::::::::::::::::::::::::::::::::::::::
277 00000140 ; Add for Power Management
278 00000140 ; - - - - - - - - - - - - - - - - - - - - - - -
279 00000140 e31a0002 tst r10, #0x2
280 00000144 0a000021 beq BringUpWinCE ; Normal Mode Booting
281 00000148
282 00000148 ; Recover Process : Starting Point
283 00000148
284 00000148 ; 1. Checksum Calculation saved Data
285 00000148
286 00000148 e59f50c8 ldr r5, =SLEEPDATA_BASE_PHYSICAL ; pointer to physical address of reserved Sleep mode info data structure
287 0000014c
288 0000014c e1a03005 mov r3, r5 ; pointer for checksum calculation
289 00000150 e3a02000 mov r2, #0
290 00000154 e3a00019 ldr r0, =SLEEPDATA_SIZE ; get size of data structure to do checksum on
291 00000158 40
292 00000158 e4931004 ldr r1, [r3], #4 ; pointer to SLEEPDATA
293 0000015c e2011001 and r1, r1, #0x1
294 00000160 e1a01f81 mov r1, r1, LSL #31
295 00000164 e18110a1 orr r1, r1, r1, LSR #1
296 00000168 e0822001 add r2, r2, r1
297 0000016c e2500001 subs r0, r0, #1 ; dec the count
298 00000170 1afffff8 bne %b40 ; loop till done
299 00000174
300 00000174 e59f00a0 ldr r0,=GSTATUS3
301 00000178 e5903000 ldr r3, [r0] ; get the Sleep data checksum from the Power Manager Scratch p
ad register
302 0000017c e1320003 teq r2, r3 ; compare to what we saved before going to sleep
303 00000180 1a000012 bne BringUpWinCE ; bad news - do a cold boot
304 00000184
305 00000184 ; 2. MMU Enable
306 00000184
307 00000184 e595a00c ldr r10, [r5, #SleepState_MMUDOMAIN] ; load the MMU domain access info
308 00000188 e5959008 ldr r9, [r5, #SleepState_MMUTTB] ; load the MMU TTB info
309 0000018c e5958004 ldr r8, [r5, #SleepState_MMUCTL] ; load the MMU control info
310 00000190 e5957000 ldr r7, [r5, #SleepState_WakeAddr ] ; load the LR address
311 00000194 e1a00000 nop
312 00000198 e1a00000 nop
313 0000019c e1a00000 nop
314 000001a0 e1a00000 nop
315 000001a4 e1a00000 nop
316 000001a8
317 000001a8 ; if software reset
318 000001a8 e3a0130e mov r1, #0x38000000
319 000001ac e1310007 teq r1, r7
320 000001b0 1a000000 bne %f1
321 000001b4 eb000005 bl BringUpWinCE
322 000001b8
323 000001b8 ; wakeup routine
324 000001b8 1
325 000001b8 ee03af10 mcr p15, 0, r10, c3, c0, 0 ; setup access to domain 0
326 000001bc ee029f10 mcr p15, 0, r9, c2, c0, 0 ; PT address
327 000001c0 ee080f17 mcr p15, 0, r0, c8, c7, 0 ; flush I+D TLBs
328 000001c4 ee018f10 mcr p15, 0, r8, c1, c0, 0 ; restore MMU control
329 000001c8
330 000001c8 ; 3. Jump to Kernel Image's fw.s(Awake_address)
331 000001c8 e1a0f007 mov pc, r7 ; & jump to new virtual address (back up Power management sta
ck)
332 000001cc e1a00000 nop
333 000001d0
334 000001d0 ; - - - - - - - - - - - - - - - - - - - - - - -
335 000001d0 ; Add for Power Management
336 000001d0 ; :::::::::::::::::::::::::::::::::::::::::::::
337 000001d0
338 000001d0 BringUpWinCE
339 000001d0
340 000001d0 e59f0048 ldr r0, = GPFDAT
341 000001d4 e3a01060 mov r1, #0x60
342 000001d8 e5801000 str r1, [r0]
343 000001dc
344 000001dc e28f0074 add r0, pc, #OEMAddressTable - (. + 8)
345 000001e0
346 000001e0 eb000000 bl KernelStart
347 000001e4
348 000001e4
349 000001e4 56000050 *literal pool: constant
349 000001e8 000055aa *literal pool: constant
349 000001ec 4a000008 *literal pool: constant
349 000001f0 4a00001c *literal pool: constant
349 000001f4 000007ff *literal pool: constant
349 000001f8 4a000004 *literal pool: constant
349 000001fc 4c000014 *literal pool: constant
349 00000200 4c000004 *literal pool: constant
349 00000204 000a1031 *literal pool: constant
349 00000208 4c000008 *literal pool: constant
349 0000020c 00048032 *literal pool: constant
349 00000210 560000b4 *literal pool: constant
349 00000214 56000080 *literal pool: constant
349 00000218 30008000 *literal pool: constant
349 0000021c 560000b8 *literal pool: constant
349 00000220 56000054 *literal pool: constant
349 000001e4 LTORG
350 00000224
351 00000224 SMRDATA DATA
352 00000224 2211d120 DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<2
8))
353 00000228 00000700 DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
354 0000022c 00000700 DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
355 00000230 00000700 DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
356 00000234 00000700 DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
357 00000238 00000700 DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
358 0000023c 00000700 DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
359 00000240 00018005 DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
360 00000244 00018005 DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
361 00000248 008e0459 DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
362 0000024c 000000b2 DCD 0xB2 ;SCLK power sa
ving mode, BANKSIZE 128M/128M
363 00000250 00000030 DCD 0x30 ;MRSR6 CL=3clk
364 00000254 00000030 DCD 0x30 ;MRSR7
365 00000258
366 00000258
367 00000258 INCLUDE map.a
1 00000258 ; TITLE("P2 Firmware Initialization")
2 00000258 ;++
3 00000258 ;
4 00000258 ; Copyright (c) 2001. Samsung Electronics, co. ltd All rights reserved.
5 00000258 ;
6 00000258 ; Module Name:
7 00000258 ;
8 00000258 ; map920.h
9 00000258 ;
10 00000258 ; Abstract:
11 00000258 ;
12 00000258 ; This module contains the OEM memory map for the S3c2410
13 00000258 ;
14 00000258 ;--
15 00000258
16 00000258
17 00000258 ;
18 00000258 ; OEMAddressTable defines the mapping from the 4GB physical address space
19 00000258 ; to the kernel's 512MB "un-mapped" spaces. The kernel will create two ranges
20 00000258 ; of virtual addresses from this table. One from 0x80000000 to 0x9FFFFFFF which
21 00000258 ; has caching & buffering enabled and one from 0xA0000000 to 0xBFFFFFFF which
22 00000258 ; has the cache & buffering disabled.
23 00000258 ;
24 00000258 ; Each entry in the table consists of the Virtual Base Address to map to,
25 00000258 ; the Physical Base Address to map from, and the number of megabytes to map.
26 00000258 ;
27 00000258 ; The order of the entries is arbitrary, but DRAM should be placed first for
28 00000258 ; optimal performance. The table is zero-terminated, so the last entry MUST
29 00000258 ; be all zeroes.
30 00000258 ;
31 00000258
32 00000258 ; Mapped for S3C2400X01
33 00000258
34 00000258 EXPORT OEMAddressTable[DATA]
35 00000258
36 00000258 OEMAddressTable
37 00000258 ;;;-------------------------------------------------------------
38 00000258 ;;; Virt Addr Phys Addr MB
39 00000258 ;;;-------------------------------------------------------------
40 00000258 ;DCD 0x80000000, 0x32000000, 32 ; 32 MB DRAM BANK 0
41 00000258 8c000000 DCD 0x8C000000, 0x08000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 1
08000000
00000020
42 00000264 84000000 DCD 0x84000000, 0x10000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 2
10000000
00000020
43 00000270 86000000 DCD 0x86000000, 0x18000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 3
18000000
00000020
44 0000027c 88000000 DCD 0x88000000, 0x20000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 4
20000000
00000020
45 00000288 8a000000 DCD 0x8A000000, 0x28000000, 32 ; 32 MB SROM(SRAM/ROM) BANK 5
28000000
00000020
46 00000294 80000000 DCD 0x80000000, 0x30000000, 64 ; 32 MB DRAM BANK 0
30000000
00000040
47 000002a0 90800000 DCD 0x90800000, 0x48000000, 1 ; Memory control register
48000000
00000001
48 000002ac 90900000 DCD 0x90900000, 0x49000000, 1 ; USB Host register
49000000
00000001
49 000002b8 90a00000 DCD 0x90A00000, 0x4A000000, 1 ; Interrupt Control register
4a000000
00000001
50 000002c4 90b00000 DCD 0x90B00000, 0x4B000000, 1 ; DMA control register
4b000000
00000001
51 000002d0 90c00000 DCD 0x90C00000, 0x4C000000, 1 ; Clock & Power register
4c000000
00000001
52 000002dc 90d00000 DCD 0x90D00000, 0x4D000000, 1 ; LCD control register
4d000000
00000001
53 000002e8 90e00000 DCD 0x90E00000, 0x4E000000, 1 ; NAND flash control register
4e000000
00000001
54 000002f4 91000000 DCD 0x91000000, 0x50000000, 1 ; UART control register
50000000
00000001
55 00000300 91100000 DCD 0x91100000, 0x51000000, 1 ; PWM timer register
51000000
00000001
56 0000030c 91200000 DCD 0x91200000, 0x52000000, 1 ; USB device register
52000000
00000001
57 00000318 91300000 DCD 0x91300000, 0x53000000, 1 ; Watchdog Timer register
53000000
00000001
58 00000324 91400000 DCD 0x91400000, 0x54000000, 1 ; IIC control register
54000000
00000001
59 00000330 91500000 DCD 0x91500000, 0x55000000, 1 ; IIS control register
55000000
00000001
60 0000033c 91600000 DCD 0x91600000, 0x56000000, 1 ; I/O Port register
56000000
00000001
61 00000348 91700000 DCD 0x91700000, 0x57000000, 1 ; RTC control register
57000000
00000001
62 00000354 91800000 DCD 0x91800000, 0x58000000, 1 ; A/D convert register
58000000
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